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[CI] Disable MSR_IA32_CR_PAT validation for now. It can be reenabled in the future if needed. On x86/AMD64 kernel might reconfigure MTRR after CPU is being put online which might be problematic for S3/S4 state.

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This commit is contained in:
Adam_pi3 2019-11-30 21:20:57 -05:00
parent 196266c5ed
commit bbd126efa7
2 changed files with 3 additions and 2 deletions
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3
src/modules/database/arch/x86/p_x86_metadata.c
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@ -236,6 +236,7 @@ void p_dump_x86_metadata(void *_p_arg) {
/* MSR_IA32_CR_PAT */
// Try reading at least 3 times before give up in case of error...
/*
P_MSR_READ_COUNT(3,p_arg[p_curr_cpu].p_MSR_IA32_CR_PAT,MSR_IA32_CR_PAT);
if (!p_arg[p_curr_cpu].p_MSR_IA32_CR_PAT) {
@ -248,7 +249,7 @@ void p_dump_x86_metadata(void *_p_arg) {
p_debug_log(P_LKRG_STRONG_DBG,
"<p_dump_IDT_MSR> CPU:[%d] MSR: MSR_IA32_CR_PAT[0x%llx] address in db[%p]\n",
p_curr_cpu,p_arg[p_curr_cpu].p_MSR_IA32_CR_PAT,&p_arg[p_curr_cpu].p_MSR_IA32_CR_PAT);
*/
/* MSR_IA32_APICBASE */
// Try reading at least 3 times before give up in case of error...

2
src/modules/database/arch/x86/p_x86_metadata.h
View file

@ -85,7 +85,7 @@ typedef struct p_CPU_metadata_hash_mem {
u64 p_MSR_IA32_SYSENTER_EIP; // 0x00000176
/* MSR PAT */
u64 p_MSR_IA32_CR_PAT; // 0x00000277
// u64 p_MSR_IA32_CR_PAT; // 0x00000277
/* MSR APIC */
u64 p_MSR_IA32_APICBASE; // 0x0000001b