Work around missing std::hardware_destructive_interference_size.
Use new CPPCORO_CPU_CACHE_LINE instead. Clang/libc++ doesn't define this symbol so just use a constant on platforms other than MSVC.
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@ -143,4 +143,11 @@
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# define CPPCORO_CPU_64BIT 0
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#endif
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#if CPPCORO_COMPILER_MSVC
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# define CPPCORO_CPU_CACHE_LINE std::hardware_destructive_interference_size
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#else
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// On most architectures we can assume a 64-byte cache line.
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# define CPPCORO_CPU_CACHE_LINE 64
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#endif
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#endif
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@ -5,6 +5,7 @@
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#ifndef CPPCORO_MULTI_PRODUCER_SEQUENCER_HPP_INCLUDED
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#define CPPCORO_MULTI_PRODUCER_SEQUENCER_HPP_INCLUDED
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#include <cppcoro/config.hpp>
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#include <cppcoro/sequence_barrier.hpp>
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#include <cppcoro/sequence_range.hpp>
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#include <cppcoro/sequence_traits.hpp>
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@ -84,10 +85,10 @@ namespace cppcoro
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const std::size_t m_sequenceMask;
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const std::unique_ptr<std::atomic<SEQUENCE>[]> m_published;
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alignas(std::hardware_destructive_interference_size)
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alignas(CPPCORO_CPU_CACHE_LINE)
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std::atomic<SEQUENCE> m_nextToClaim;
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alignas(std::hardware_destructive_interference_size)
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alignas(CPPCORO_CPU_CACHE_LINE)
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mutable std::atomic<multi_producer_sequencer_wait_operation<SEQUENCE, TRAITS>*> m_awaiters;
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#if CPPCORO_COMPILER_MSVC
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@ -115,11 +115,11 @@ namespace cppcoro
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#endif
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// First cache-line is written to by the producer only
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alignas(std::hardware_destructive_interference_size)
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alignas(CPPCORO_CPU_CACHE_LINE)
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std::atomic<SEQUENCE> m_lastPublished;
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// Second cache-line is written to by both the producer and consumers
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alignas(std::hardware_destructive_interference_size)
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alignas(CPPCORO_CPU_CACHE_LINE)
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mutable std::atomic<awaiter_t*> m_awaiters;
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#if CPPCORO_COMPILER_MSVC
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@ -5,6 +5,7 @@
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#ifndef CPPCORO_SINGLE_PRODUCER_SEQUENCER_HPP_INCLUDED
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#define CPPCORO_SINGLE_PRODUCER_SEQUENCER_HPP_INCLUDED
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#include <cppcoro/config.hpp>
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#include <cppcoro/sequence_barrier.hpp>
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#include <cppcoro/sequence_range.hpp>
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@ -97,7 +98,7 @@ namespace cppcoro
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const sequence_barrier<SEQUENCE, TRAITS>& m_consumerBarrier;
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const std::size_t m_bufferSize;
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alignas(std::hardware_destructive_interference_size)
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alignas(CPPCORO_CPU_CACHE_LINE)
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SEQUENCE m_nextToClaim;
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sequence_barrier<SEQUENCE, TRAITS> m_producerBarrier;
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