This commit is contained in:
Miloslav Ciz 2021-10-03 17:54:21 -05:00
parent 13b27e8cda
commit b7199dca19
1 changed files with 2 additions and 3 deletions

View File

@ -7,8 +7,7 @@ x86
- variable instruction size (usually 2-3 bytes)
- little endian
- partially "open"
patented anymore
- 16, 32, 64 bit
- 16, 32, 64 bit versions
- supports (usually as extension) float, SIMD, MMX, SSE, ...
- modes:
- real: 20b segmented addr. (~1 Mib RAM), no mem. protection
@ -78,7 +77,7 @@ ARM (advanced RISC machines)
--------------------------------------------------------------------------------
- family of instruction sets (ARMv1, ARMv2, ARMv3, ...)
- mainly for embedded, simple, low energy sonsumption and heat
- arch.: register-register
- arch.: load-store
- "proprietary"
- fixed instr. length (32b), BUT there is also a Thumb subset that encodes
instrs. as 16b (smaller code but fewer instructions), and Thumb2 (variable