Update
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Miloslav Ciz
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x86
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- a family of inst. sets (not a single one), extended with back. compat.
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- mainly for desktops
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- arch.: register-memory
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- CISC, 3000+ instructions total (~1000 mnemonics)
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- variable instruction size (usually 2-3 bytes)
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- little endian
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- partially "open"
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patented anymore
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- 16, 32, 64 bit
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- supports (usually as extension) float, SIMD, MMX, SSE, ...
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- modes:
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- real: 20b segmented addr. (~1 Mib RAM), no mem. protection
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- unreal: weird
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- protected: 16 MB (1 GB) of physical (virtual) RAM, protected memory
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- long
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- ...
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- bloat, implementations use speculation, reordering, prediction, microcode,
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pipelines etc.
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- registers:
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general purpose registers:
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64b | RAX | RBX | RCX | RDX |
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32b | | EAX | | EBX | | CAX | | EDX |
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16b | | | AX | | | BX | | | CX | | | DX |
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8b | | |AH AL | | |BH BL | | |CH CL | | |DH DL |
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other registers:
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(E/R)FLAGS <- various flags set by operations
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CF PF AF ZF SF TF IF DF OF ...
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carry parity aux. zero sign trap int. dir. overflow
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(E/R)SP <- stack pointer
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(E/R)BP <- stack base pointer
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(E/R)IP <- instruciton poitner
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(E/R)SI <- source pointer
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(E/R)DI <- destination pointer
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CS <- code pointer \
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DS <- data pointer | segment
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SS <- stack | registers
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ES,FS,GS <- extra pointer /
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- instruction format:
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- 0 to 4 prefix bytes modifying the instruction
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- 1 to 2 bytes opcode identifying the instruction
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- 0 to 1 bytes describing the operands (memory/registers)
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- 0 to 1 bytes of a weird "scaled index byte"
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- 0 to 4 memory displacement bytes, specify the address offset
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- 0 to 4 immediate bytes, specify a constant value
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- basic instructions:
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ADD add
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ADC add with carry
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CALL call procedure (pushes EIP and jumps)
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DEC decrement
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DIV unsigned divide
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IDIV signed divide
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IMUL signed multiply
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INC increment
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JNE, JNZ, JZ, ... jump if condition (not equal, not zero, zero, ...)
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JMP unconditional jump
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MOV move (copy data)
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MUL unsigned multiply
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NEG negation (two's complement)
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NOP no operation
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POP pop from stack
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PUSH push onto stack
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ROL rotate left
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SHR shift right
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ARM (advanced RISC machines)
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--------------------------------------------------------------------------------
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- family of instruction sets (ARMv1, ARMv2, ARMv3, ...)
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- mainly for embedded, simple, low energy sonsumption and heat
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- arch.: register-register
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- "proprietary"
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- fixed instr. length (32b), BUT there is also a Thumb subset that encodes
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instrs. as 16b (smaller code but fewer instructions), and Thumb2 (variable
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instr. size)
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- little endian, can be switched to big
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- RISC, 232 instructions (~50 mnemonics)
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- 32b, 64b
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- mostly 1 CPI
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- modes:
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- user: unpriviledged (can't do certain things)
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- supervisor: priviledged
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- undefined: after undefined inst.
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- abort: after memory access violation
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- ...
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- doesn't have divide instruction!
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- implementaitons don't use microcode, are often simple without caches etc.
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- instruction format:
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| operand |dst|src||opc||0|co |
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| 2 |reg|reg||ode||0| nd|
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--------........--------........
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Almost all instruciton can have a condition.
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- registers:
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- all 32 bit
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- general purpose: R0 - R12
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- stack pointer: R13
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- link register: R14 (function return address)
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- program counter: R15
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- flags: CPSR (CPU mode, thumb, endian, zero, carry, ...)
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- basic instructions:
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ADC add with carry
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ADD add
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AND and operation
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B, BNE, BEQ, ... branch if (always, not equal, equal, ...)
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CMP compare
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LDR load memory to register
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MOV move register/constant to register
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MUL multiply
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STR store register to memory
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SWI software interrupt
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RISC-V
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--------------------------------------------------------------------------------
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POWER PC
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--------------------------------------------------------------------------------
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