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* Timers: CCR made array

This commit is contained in:
Vovanium 2024-01-24 19:49:36 +03:00
parent c4bf0a951f
commit 38c8bfff81
1 changed files with 6 additions and 12 deletions
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18
library/source/f4/stm32-timers.ads
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@ -9,6 +9,8 @@ package STM32.Timers is
-- timers are seem to be identical across the whole STM32F4 family. -- timers are seem to be identical across the whole STM32F4 family.
-- Some SVD differences are noted here. -- Some SVD differences are noted here.
type Channel_Index is range 1 .. 4;
-- --
-- CR1 -- CR1
-- --
@ -382,6 +384,8 @@ package STM32.Timers is
type Count_Register is range 0 .. 2**32 - 1 with Size => 32; type Count_Register is range 0 .. 2**32 - 1 with Size => 32;
type Count_Register_Array is array (Channel_Index) of Count_Register;
-- TIM: 1,3,4,8-14 2,5 -- TIM: 1,3,4,8-14 2,5
-- bits 16 32 -- bits 16 32
@ -564,14 +568,7 @@ package STM32.Timers is
pragma Volatile_Full_Access (ARR); pragma Volatile_Full_Access (ARR);
RCR : Repetition_Counter_Register; RCR : Repetition_Counter_Register;
pragma Volatile_Full_Access (RCR); pragma Volatile_Full_Access (RCR);
CCR1 : Count_Register; CCR : Count_Register_Array;
pragma Volatile_Full_Access (CCR1);
CCR2 : Count_Register;
pragma Volatile_Full_Access (CCR2);
CCR3 : Count_Register;
pragma Volatile_Full_Access (CCR3);
CCR4 : Count_Register;
pragma Volatile_Full_Access (CCR4);
BDTR : Break_and_Dead_Time_Register; BDTR : Break_and_Dead_Time_Register;
pragma Volatile_Full_Access (BDTR); pragma Volatile_Full_Access (BDTR);
DCR : DMA_Control_Register; DCR : DMA_Control_Register;
@ -595,10 +592,7 @@ package STM32.Timers is
PSC at 16#28# range 0 .. 15; -- + + + + + + + PSC at 16#28# range 0 .. 15; -- + + + + + + +
ARR at 16#2C# range 0 .. 31; -- 16 32 16 16 16 16 16 ARR at 16#2C# range 0 .. 31; -- 16 32 16 16 16 16 16
RCR at 16#30# range 0 .. 15; -- + - - - - - - RCR at 16#30# range 0 .. 15; -- + - - - - - -
CCR1 at 16#34# range 0 .. 31; -- + 32 16 16 16 16 - CCR at 16#34# range 0 .. 32 * 4 - 1;-- + 4*32 4*16 2*16 1*16 1*16 -
CCR2 at 16#38# range 0 .. 31; -- + 32 16 16 - - -
CCR3 at 16#3C# range 0 .. 31; -- + 32 16 - - - -
CCR4 at 16#40# range 0 .. 31; -- + 32 16 - - - -
BDTR at 16#44# range 0 .. 15; -- + - - - - - - BDTR at 16#44# range 0 .. 15; -- + - - - - - -
DCR at 16#48# range 0 .. 15; -- + + + - - - - DCR at 16#48# range 0 .. 15; -- + + + - - - -
DMAR at 16#4C# range 0 .. 31; -- + + + - - - - DMAR at 16#4C# range 0 .. 31; -- + + + - - - -