639 lines
24 KiB
Ada
639 lines
24 KiB
Ada
with STM32.Address_Map;
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-- Timers, Including Basic, General Purpose (both kids) and Advanced Control
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package STM32.Timers is
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-- There's some differences in SVD files between devices,
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-- however according to reference manuals
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-- timers are seem to be identical across the whole STM32F4 family.
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-- Some SVD differences are noted here.
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--
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-- CR1
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--
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type Count_Direction is (
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Count_Up,
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Count_Down) with Size => 1;
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type Align_Mode is (
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Edge_Aligned, -- Counts only in direction specified in DIR
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Center_Aligned_OC_Down, -- Counts in both directions alternatively,
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-- OC interrupts are set when counting down
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Center_Aligned_OC_Up, -- Counts in both directions alternatively,
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-- OC interrupts are set when counting up
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Center_Aligned_OC_Both) -- Counts in both directions alternatively,
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-- OC interrupts are set when counting in either direction
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with Size => 2;
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type Update_Request_Source is (
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Any_Source,
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Counter_Overflow) with Size => 1;
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type Sampling_Clock is new Logarithmic range Value_1 .. Value_8 with Size => 2;
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type Control_Register_1 is record
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CEN : Boolean := False; -- Counter enable
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UDIS : Boolean := False; -- Update disable
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URS : Update_Request_Source := Any_source; -- Update request source
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OPM : Boolean := False; -- One-pulse mode
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DIR : Count_Direction := Count_Up; -- Direction
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CMS : Align_Mode := Edge_Aligned; -- Center-aligned mode
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ARPE : Boolean := False; -- Auto-reload preload enable
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CKD : Sampling_Clock := Value_1; -- Clock division
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Unused_10 : Unused_1_Bit := 0;
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UIFREMAP : Boolean := False; -- UIF status bit remapping
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Unused_12 : Unused_4_Bits := 0;
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end record with Size => 16;
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for Control_Register_1 use record -- TIM: 1,2-5,8 9-14 6,7
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CEN at 0 range 0 .. 0; -- + + +
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UDIS at 0 range 1 .. 1; -- + + +
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URS at 0 range 2 .. 2; -- + + +
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OPM at 0 range 3 .. 3; -- + + +
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DIR at 0 range 4 .. 4; -- + - -
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CMS at 0 range 5 .. 6; -- + - -
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ARPE at 0 range 7 .. 7; -- + + +
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CKD at 0 range 8 .. 9; -- + + -
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Unused_10 at 0 range 10 .. 10;
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UIFREMAP at 0 range 11 .. 11; -- - - ?
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Unused_12 at 0 range 12 .. 15;
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end record;
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-- Note: UIFREMAP bit is not documented but exist in SVD of STM32F412/413.
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-- This may be a bug in SVD or not yet documented feature.
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--
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-- CR2
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--
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type CCPC_Update is (
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COMG_Only,
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COMG_or_TRGI_Edge) with Size => 1;
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type CC_DMA_Request is (
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DMA_on_CC,
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DMA_on_Update) with Size => 1;
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type Master_Mode is (
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Master_Reset,
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Master_Enable,
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Master_Update,
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Master_Compare_Pulse,
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Master_Compare_OC1REF,
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Master_Compare_OC2REF,
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Master_Compare_OC3REF,
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Master_Compare_OC4REF) with Size => 3;
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-- In TIM6, TIM7 only Master_Reset, Master_Enable and Master_Enable values allowed.
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type TI1_Connection is (
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Channel_1_Only,
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Channels_1_2_3_Xored) with Size => 1;
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type Control_Register_2 is record
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CCPC : Boolean := False; -- Capture/compare preloaded
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Unused_1 : Unused_1_Bit := 0;
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CCUS : CCPC_Update := COMG_Only; -- Capture/compare control update
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CCDS : CC_DMA_Request := DMA_on_CC; -- Capture/compare DMA
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MMS : Master_Mode := Master_Reset; -- Master mode selection
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TI1S : TI1_Connection := Channel_1_Only; -- TI1 selection
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OIS1 : Boolean := False; -- Output Idle state 1
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OIS1N : Boolean := False; -- Output Idle state 1
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OIS2 : Boolean := False; -- Output Idle state 2
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OIS2N : Boolean := False; -- Output Idle state 2
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OIS3 : Boolean := False; -- Output Idle state 3
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OIS3N : Boolean := False; -- Output Idle state 3
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OIS4 : Boolean := False; -- Output Idle state 4
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Unused_15 : Unused_1_Bit := 0;
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end record with Size => 16;
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for Control_Register_2 use record -- TIM: 1,8 2-5 6,7 9
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CCPC at 0 range 0 .. 0; -- + - -
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Unused_1 at 0 range 1 .. 1;
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CCUS at 0 range 2 .. 2; -- + - -
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CCDS at 0 range 3 .. 3; -- + + -
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MMS at 0 range 4 .. 6; -- + + + ?
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TI1S at 0 range 7 .. 7; -- + + -
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OIS1 at 0 range 8 .. 8; -- + - -
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OIS1N at 0 range 9 .. 9; -- + - -
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OIS2 at 0 range 10 .. 10; -- + - -
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OIS2N at 0 range 11 .. 11; -- + - -
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OIS3 at 0 range 12 .. 12; -- + - -
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OIS3N at 0 range 13 .. 13; -- + - -
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OIS4 at 0 range 14 .. 14; -- + - -
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Unused_15 at 0 range 15 .. 15;
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end record;
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--
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-- SMCR
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--
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type Slave_Mode is (
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Slave_Mode_Disabled, --
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Slave_Encoder_Mode_1, --
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Slave_Encoder_Mode_2, --
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Slave_Encoder_Mode_3, --
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Slave_Reset, -- Rising edge of TRGI reinitializes the counter and update the registers
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Slave_Gate, -- Counting runs when TRGI is high else stops.
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Slave_Trigger, -- Counting starts on a rising edge of TRGI (but not reset).
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Slave_Clock) -- Counting rising edges of TRGI.
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with Size => 3;
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-- Slave_Encoder_Mode_(1,2,3) not present in GPT9
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type Trigger_Select is (
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Internal_Trigger_0,
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Internal_Trigger_1,
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Internal_Trigger_2,
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Internal_Trigger_3,
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TI1_Edge_Detector,
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Filtered_Input_1,
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Filtered_Input_2,
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External_Trigger)
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with Size => 3;
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-- External trigger not present in TIM9, TIM 12
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type Trigger_Filter is (
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DTS_Not_Filtered,
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CK_INT_Filter_2,
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CK_INT_Filter_4,
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CK_INT_Filter_8,
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DTS_DIV_2_Filter_6,
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DTS_DIV_2_Filter_8,
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DTS_DIV_4_Filter_6,
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DTS_DIV_4_Filter_8,
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DTS_DIV_8_Filter_6,
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DTS_DIV_8_Filter_8,
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DTS_DIV_16_Filter_5,
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DTS_DIV_16_Filter_6,
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DTS_DIV_16_Filter_8,
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DTS_DIV_32_Filter_5,
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DTS_DIV_32_Filter_6,
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DTS_DIV_32_Filter_8) with Size => 4;
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type Trigger_Prescaler is new Logarithmic range Value_1 .. Value_8 with Size => 2;
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type External_Trigger_Polarity is (Non_Inverted, Inverted) with Size => 1;
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type Slave_Mode_Control_Register is record
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SMS : Slave_Mode := Slave_Mode_Disabled; -- Slave mode selection
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Unused_3 : Unused_1_Bit := 0;
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TS : Trigger_Select := Internal_Trigger_0; -- Trigger selection
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MSM : Boolean := False; -- Master/Slave mode
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ETF : Trigger_Filter := DTS_Not_Filtered; -- External trigger filter
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ETPS : Trigger_Prescaler := Value_1; -- External trigger prescaler
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ECE : Boolean := False; -- External clock enable
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ETP : External_Trigger_Polarity := Non_Inverted; -- External trigger polarity
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end record with Size => 16;
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for Slave_Mode_Control_Register use record -- TIM: 1,2-5,8 9,12
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SMS at 0 range 0 .. 2; -- + +
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Unused_3 at 0 range 3 .. 3;
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TS at 0 range 4 .. 6; -- + +
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MSM at 0 range 7 .. 7; -- + +
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ETF at 0 range 8 .. 11; -- + -
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ETPS at 0 range 12 .. 13; -- + -
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ECE at 0 range 14 .. 14; -- + -
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ETP at 0 range 15 .. 15; -- + -
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end record;
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--
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-- DIER
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--
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type DMA_Interrupt_Enable_Register is record
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UIE : Boolean := False; -- Update interrupt enable
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CC1IE : Boolean := False; -- Capture/Compare 1 interrupt
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CC2IE : Boolean := False; -- Capture/Compare 2 interrupt
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CC3IE : Boolean := False; -- Capture/Compare 3 interrupt
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CC4IE : Boolean := False; -- Capture/Compare 4 interrupt
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COMIE : Boolean := False; -- COM interrupt enable
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TIE : Boolean := False; -- Trigger interrupt enable
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BIE : Boolean := False; -- Break interrupt enable
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UDE : Boolean := False; -- Update DMA request enable
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CC1DE : Boolean := False; -- Capture/Compare 1 DMA request
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CC2DE : Boolean := False; -- Capture/Compare 2 DMA request
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CC3DE : Boolean := False; -- Capture/Compare 3 DMA request
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CC4DE : Boolean := False; -- Capture/Compare 4 DMA request
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COMDE : Boolean := False; -- COM DMA request enable
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TDE : Boolean := False; -- Trigger DMA request enable
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Unused_15 : Unused_1_Bit := 0;
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end record with Size => 16;
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for DMA_Interrupt_Enable_Register use record -- TIM: 1,8 2-5 9,12 10,11,13,14 6,7
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UIE at 0 range 0 .. 0; -- + + + + +
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CC1IE at 0 range 1 .. 1; -- + + + + -
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CC2IE at 0 range 2 .. 2; -- + + + - -
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CC3IE at 0 range 3 .. 3; -- + + - - -
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CC4IE at 0 range 4 .. 4; -- + + - - -
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COMIE at 0 range 5 .. 5; -- + - - - -
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TIE at 0 range 6 .. 6; -- + + + - -
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BIE at 0 range 7 .. 7; -- + - - - -
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UDE at 0 range 8 .. 8; -- + + - - +
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CC1DE at 0 range 9 .. 9; -- + + - - -
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CC2DE at 0 range 10 .. 10; -- + + - - -
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CC3DE at 0 range 11 .. 11; -- + + - - -
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CC4DE at 0 range 12 .. 12; -- + + - - -
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COMDE at 0 range 13 .. 13; -- + - - - -
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TDE at 0 range 14 .. 14; -- + + - - -
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Unused_15 at 0 range 15 .. 15;
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end record;
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--
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-- SR
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--
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type Status_Register is record
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UIF : Boolean := False; -- Update interrupt flag
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CC1IF : Boolean := False; -- Capture/compare 1 interrupt
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CC2IF : Boolean := False; -- Capture/Compare 2 interrupt
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CC3IF : Boolean := False; -- Capture/Compare 3 interrupt
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CC4IF : Boolean := False; -- Capture/Compare 4 interrupt
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COMIF : Boolean := False; -- COM interrupt flag
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TIF : Boolean := False; -- Trigger interrupt flag
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BIF : Boolean := False; -- Break interrupt flag
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Unused_8 : Unused_1_Bit := 0;
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CC1OF : Boolean := False; -- Capture/Compare 1 overcapture
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CC2OF : Boolean := False; -- Capture/compare 2 overcapture
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CC3OF : Boolean := False; -- Capture/Compare 3 overcapture
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CC4OF : Boolean := False; -- Capture/Compare 4 overcapture
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Unused_13 : Unused_3_Bits := 0;
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end record with Size => 16;
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for Status_Register use record -- TIM: 1,8 2-5 9,12 10,11,13,14 6,7
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UIF at 0 range 0 .. 0; -- + + + + +
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CC1IF at 0 range 1 .. 1; -- + + + + -
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CC2IF at 0 range 2 .. 2; -- + + + - -
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CC3IF at 0 range 3 .. 3; -- + + - - -
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CC4IF at 0 range 4 .. 4; -- + + - - -
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COMIF at 0 range 5 .. 5; -- + - - - -
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TIF at 0 range 6 .. 6; -- + + + - -
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BIF at 0 range 7 .. 7; -- + - - - -
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Unused_8 at 0 range 8 .. 8;
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CC1OF at 0 range 9 .. 9; -- + + + + -
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CC2OF at 0 range 10 .. 10; -- + + + - -
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CC3OF at 0 range 11 .. 11; -- + + - - -
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CC4OF at 0 range 12 .. 12; -- + + - - -
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Unused_13 at 0 range 13 .. 15;
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end record;
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--
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-- EGR
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--
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type Event_Generation_Register is record
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UG : Boolean := False; -- Update generation
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CC1G : Boolean := False; -- Capture/compare 1
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CC2G : Boolean := False; -- Capture/compare 2
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CC3G : Boolean := False; -- Capture/compare 3
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CC4G : Boolean := False; -- Capture/compare 4
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COMG : Boolean := False; -- Capture/Compare control update
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TG : Boolean := False; -- Trigger generation
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BG : Boolean := False; -- Break generation
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Unused_8 : Unused_8_Bits := 0;
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end record with Size => 16;
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for Event_Generation_Register use record -- TIM: 1,8 2-5 9,12 10,11,13,14 6,7
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UG at 0 range 0 .. 0; -- + + + + +
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CC1G at 0 range 1 .. 1; -- + + + + -
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CC2G at 0 range 2 .. 2; -- + + + - -
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CC3G at 0 range 3 .. 3; -- + + - - -
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CC4G at 0 range 4 .. 4; -- + + - - -
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COMG at 0 range 5 .. 5; -- + - - - -
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TG at 0 range 6 .. 6; -- + + + - -
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BG at 0 range 7 .. 7; -- + - - - -
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Unused_8 at 0 range 8 .. 15;
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end record;
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--
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-- CCMRx
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--
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type CC_Direction is (
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CC_Output,
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CC_Input_Primary,
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CC_Input_Alternate,
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CC_Input_TRC) with Size => 2;
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-- CC_Input_Alternate and CC_Input_TRC is not present in TIM10, TIM11, TIM13, TIM4.
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type Compare_Mode is (
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Frozen,
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Match_Set_to_Active,
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Match_Set_to_Inactive,
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Match_Toggle,
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Force_Inactive,
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Force_Active,
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PWM_True,
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PWM_Inverted) with Size => 3;
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type CC_Mode (S : CC_Direction := CC_Output) is record
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case S is
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when CC_Output =>
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FE : Boolean := False; -- Output Compare fast
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PE : Boolean := False; -- Output Compare preload
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M : Compare_Mode := Frozen; -- Output Compare mode
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CE : Boolean := False; -- Output Compare clear
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when others =>
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PCS : Trigger_Prescaler := Value_1; -- Input capture prescaler
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F : Trigger_Filter := DTS_Not_Filtered; -- Input capture filter
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end case;
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end record with Size => 8;
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for CC_Mode use record -- TIM: 1-5,8 9,12 10,11,13,14
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S at 0 range 0 .. 1; -- ++++ --++ ---+
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FE at 0 range 2 .. 2; -- ++++ --++ ---+
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PE at 0 range 3 .. 3; -- ++++ --++ ---+
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M at 0 range 4 .. 6; -- ++++ --++ ---+
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CE at 0 range 7 .. 7; -- ++++ ---- ---+
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PCS at 0 range 2 .. 3; -- ++++ --++ ---+
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F at 0 range 4 .. 7; -- ++++ --++ ---+
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end record;
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type CC_Mode_Register is array (Positive range <>) of CC_Mode with Pack;
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type CC_Mode_Register_1 is new CC_Mode_Register (1 .. 2) with Size => 16;
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type CC_Mode_Register_2 is new CC_Mode_Register (3 .. 4) with Size => 16;
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--
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-- CCER
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--
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type Output_Polarity is (Active_High, Active_Low) with Size => 1;
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type CC_Enable_Channel is record
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E : Boolean := False;
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P : Output_Polarity := Active_High;
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NE : Boolean := False;
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NP : Output_Polarity := Active_High;
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end record with Size => 4;
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for CC_Enable_Channel use record
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E at 0 range 0 .. 0;
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P at 0 range 1 .. 1;
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NE at 0 range 2 .. 2;
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NP at 0 range 3 .. 3;
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end record;
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type CC_Enable_Register is array (1 .. 4) of CC_Enable_Channel with Pack, Size => 16;
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-- TIM: 1,8 2-5 9,12 10,11,13,14
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-- NN NN NN NN
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-- PEPE PEPE PEPE PEPE
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-- 1 ++++ +-++ +-++ +-++
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-- 2 ++++ +-++ +-++ ----
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-- 3 ++++ +-++ ---- ----
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-- 4 --++ +-++ ---- ----
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--
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-- CNT, ARR, CCRx
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--
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type Count_Register is range 0 .. 2**32 - 1 with Size => 32;
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-- TIM: 1,3,4,8-14 2,5
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-- bits 16 32
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-- Note: Bit 31 of CNT is declared in STM32F412/413's SVD as UIFCPY but not documented in RM.
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-- See note on CR1.
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--
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-- PSC
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--
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type Prescaler_Register is range 0 .. 2**16 - 1 with Size => 16;
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--
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-- RCR
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--
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type Repetition_Counter_Register is record
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REP : Integer range 0 .. 2**8 - 1 := 0; -- Repetition counter value
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Unused_8 : Unused_8_Bits := 0;
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end record with Size => 16;
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for Repetition_Counter_Register use record -- TIM: 1,8 2-5
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REP at 0 range 0 .. 7; -- + -
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Unused_8 at 0 range 8 .. 15;
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end record;
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--
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-- BDTR
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--
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-- Register is specific to advanced control timer
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type Break_Polarity is (
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Active_Low,
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Active_High) with Size => 1;
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type Lock_Level is new Integer range 0 .. 3 with Size => 2;
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type Dead_Time is new Integer range 0 .. 2**8 - 1;
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-- Dead time value
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-- 0nnn_nnnn => nnn_nnnn * t_DTS
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-- 10nn_nnnn => 1nnn_nnn0 * t_DTS
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-- 110n_nnnn => 1_nnnn_n000 * t_DTS
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-- 111n_nnnn => 1n_nnnn_0000 * t_DTS
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type Break_and_Dead_Time_Register is record
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DTG : Dead_Time := 0; -- Dead-time generator setup
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LOCK : Lock_Level := 0; -- Lock configuration
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OSSI : Boolean := False; -- Off-state selection for Idle
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OSSR : Boolean := False; -- Off-state selection for Run
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BKE : Boolean := False; -- Break enable
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BKP : Break_Polarity := Active_Low; -- Break polarity
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AOE : Boolean := False; -- Automatic output enable
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MOE : Boolean := False; -- Main output enable
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end record with Size => 16;
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for Break_and_Dead_Time_Register use record
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DTG at 0 range 0 .. 7;
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LOCK at 0 range 8 .. 9;
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OSSI at 0 range 10 .. 10;
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OSSR at 0 range 11 .. 11;
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BKE at 0 range 12 .. 12;
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BKP at 0 range 13 .. 13;
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AOE at 0 range 14 .. 14;
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MOE at 0 range 15 .. 15;
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end record;
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--
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-- DCR
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--
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type DMA_Address is (
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DMA_CR1,
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DMA_CR2,
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DMA_SMCR,
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DMA_DIER,
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DMA_SR,
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DMA_EGR,
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DMA_CCMR1,
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DMA_CCMR2,
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DMA_CCER,
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DMA_CNT,
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DMA_PSC,
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DMA_ARR,
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DMA_RCR,
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DMA_CCR1,
|
|
DMA_CCR2,
|
|
DMA_CCR3,
|
|
DMA_CCR4,
|
|
DMA_BDTR,
|
|
DMA_DCR,
|
|
DMA_DMAR,
|
|
DMA_OR) with Size => 5;
|
|
|
|
type DMA_Control_Register is record
|
|
DBA : DMA_Address := DMA_CR1; -- DMA base address
|
|
Unused_5 : Unused_3_Bits := 0;
|
|
DBL : Integer range 0 .. 31 := 0; -- DMA burst length
|
|
Unused_13 : Unused_3_Bits := 0;
|
|
end record with Size => 16;
|
|
for DMA_Control_Register use record
|
|
DBA at 0 range 0 .. 4;
|
|
Unused_5 at 0 range 5 .. 7;
|
|
DBL at 0 range 8 .. 12;
|
|
Unused_13 at 0 range 13 .. 15;
|
|
end record;
|
|
|
|
--
|
|
-- DMAR
|
|
--
|
|
-- TIM: 1,8 2-5 9,12
|
|
-- + + -
|
|
|
|
--
|
|
-- OR
|
|
--
|
|
|
|
type TI_Remap is (
|
|
TI_GPIO, -- Connect to GPIO
|
|
TI_LSI, -- Connect to LSI for calibration purposes
|
|
TI_LSE, -- Connext to LSE for calibration purposes
|
|
TI_RTC) -- Connect to RTC wakeup for calibration purposes
|
|
with Size => 2;
|
|
-- On TIM11, TI4_LSI and TI4_RTC values actually connect to GPIO.
|
|
|
|
type ITR1_Remap is (
|
|
ITR1_TIM8_TRGOUT, -- Connect to TIM8 TRGOUT
|
|
ITR1_PTP_Trigger_Output, -- Connect to PTP trigger output
|
|
ITR1_OTG_FS_SOF, -- Connect to OTG FS SOF
|
|
ITR1_OTG_HS_SOF) -- Connect to OTG HS SOF
|
|
with Size => 2;
|
|
|
|
type Option_Register is record
|
|
TI1_RMP : TI_Remap := TI_GPIO; -- TIM11 Input 1 remap
|
|
Unused_2 : Unused_4_Bits := 0;
|
|
TI4_RMP : TI_Remap := TI_GPIO; -- TIM5 Input 4 remap
|
|
Unused_8 : Unused_2_Bits := 0;
|
|
ITR1_RMP : ITR1_Remap := ITR1_TIM8_TRGOUT; -- TIM2 Internal trigger 1 remap
|
|
Unused_12 : Unused_4_Bits := 0;
|
|
end record with Size => 16;
|
|
for Option_Register use record -- TIM: 1,3,4,8-10,12-14 2 5 11
|
|
TI1_RMP at 0 range 0 .. 1; -- - - - +
|
|
Unused_2 at 0 range 2 .. 5;
|
|
TI4_RMP at 0 range 6 .. 7; -- - - + -
|
|
Unused_8 at 0 range 8 .. 9;
|
|
ITR1_RMP at 0 range 10 .. 11; -- - + - -
|
|
Unused_12 at 0 range 12 .. 15;
|
|
end record;
|
|
|
|
-- note: Register OR is named OPTR here to not clash with Ada's reserved word.
|
|
|
|
--
|
|
|
|
-- The following declaration covers all timer configurations
|
|
-- Different timers may have missing several registers, register fields, or field values,
|
|
-- and also have different register widths
|
|
-- It is up to driver software not to write them.
|
|
|
|
type Timer_Registers is record
|
|
CR1 : Control_Register_1;
|
|
pragma Volatile_Full_Access (CR1);
|
|
CR2 : Control_Register_2;
|
|
pragma Volatile_Full_Access (CR2);
|
|
SMCR : Slave_Mode_Control_Register;
|
|
pragma Volatile_Full_Access (SMCR);
|
|
DIER : DMA_Interrupt_Enable_Register;
|
|
pragma Volatile_Full_Access (DIER);
|
|
SR : Status_Register;
|
|
pragma Volatile_Full_Access (SR);
|
|
EGR : Event_Generation_Register;
|
|
pragma Volatile_Full_Access (EGR);
|
|
CCMR1 : CC_Mode_Register_1;
|
|
pragma Volatile_Full_Access (CCMR1);
|
|
CCMR2 : CC_Mode_Register_2;
|
|
pragma Volatile_Full_Access (CCMR2);
|
|
CCER : CC_Enable_Register;
|
|
pragma Volatile_Full_Access (CCER);
|
|
CNT : Count_Register;
|
|
pragma Volatile_Full_Access (CNT);
|
|
PSC : Prescaler_Register;
|
|
pragma Volatile_Full_Access (PSC);
|
|
ARR : Count_Register;
|
|
pragma Volatile_Full_Access (ARR);
|
|
RCR : Repetition_Counter_Register;
|
|
pragma Volatile_Full_Access (RCR);
|
|
CCR1 : Count_Register;
|
|
pragma Volatile_Full_Access (CCR1);
|
|
CCR2 : Count_Register;
|
|
pragma Volatile_Full_Access (CCR2);
|
|
CCR3 : Count_Register;
|
|
pragma Volatile_Full_Access (CCR3);
|
|
CCR4 : Count_Register;
|
|
pragma Volatile_Full_Access (CCR4);
|
|
BDTR : Break_and_Dead_Time_Register;
|
|
pragma Volatile_Full_Access (BDTR);
|
|
DCR : DMA_Control_Register;
|
|
pragma Volatile_Full_Access (DCR);
|
|
DMAR : Unsigned_32;
|
|
pragma Volatile_Full_Access (DMAR);
|
|
OPTR : Option_Register; -- Option register (OR in original documentation)
|
|
pragma Volatile_Full_Access (OPTR);
|
|
end record with Volatile;
|
|
for Timer_Registers use record -- TIM: 1,8 2,5 3,4 9,12 10,13,14 11 6,7
|
|
CR1 at 16#00# range 0 .. 15; -- + + + + + + +
|
|
CR2 at 16#04# range 0 .. 15; -- + + + - - - +
|
|
SMCR at 16#08# range 0 .. 15; -- + + + + - - -
|
|
DIER at 16#0C# range 0 .. 15; -- + + + + + + +
|
|
SR at 16#10# range 0 .. 15; -- + + + + + + +
|
|
EGR at 16#14# range 0 .. 15; -- + + + + + + +
|
|
CCMR1 at 16#18# range 0 .. 15; -- + + + + +- +- -
|
|
CCMR2 at 16#1C# range 0 .. 15; -- + + + - - - -
|
|
CCER at 16#20# range 0 .. 15; -- + + + + + + -
|
|
CNT at 16#24# range 0 .. 31; -- 16 32 16 16 16 16 16
|
|
PSC at 16#28# range 0 .. 15; -- + + + + + + +
|
|
ARR at 16#2C# range 0 .. 31; -- 16 32 16 16 16 16 16
|
|
RCR at 16#30# range 0 .. 15; -- + - - - - - -
|
|
CCR1 at 16#34# range 0 .. 31; -- + 32 16 16 16 16 -
|
|
CCR2 at 16#38# range 0 .. 31; -- + 32 16 16 - - -
|
|
CCR3 at 16#3C# range 0 .. 31; -- + 32 16 - - - -
|
|
CCR4 at 16#40# range 0 .. 31; -- + 32 16 - - - -
|
|
BDTR at 16#44# range 0 .. 15; -- + - - - - - -
|
|
DCR at 16#48# range 0 .. 15; -- + + + - - - -
|
|
DMAR at 16#4C# range 0 .. 31; -- + + + - - - -
|
|
OPTR at 16#50# range 0 .. 15; -- - * - - - * -
|
|
end record;
|
|
|
|
TIM1: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM1;
|
|
TIM2: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM2;
|
|
TIM3: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM3;
|
|
TIM4: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM4;
|
|
TIM5: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM5;
|
|
TIM6: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM6;
|
|
TIM7: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM7;
|
|
TIM8: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM8;
|
|
TIM9: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM9;
|
|
TIM10: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM10;
|
|
TIM11: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM11;
|
|
TIM12: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM12;
|
|
TIM13: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM13;
|
|
TIM14: aliased Timer_Registers with Volatile, Import, Address => Address_Map.TIM14;
|
|
|
|
-- In F469 TIM9,TIM12 no CR2
|
|
|
|
-- There are register fields in SVD, but Docs know nothi about:
|
|
-- in F412,F413 TIM6,7 CR1 have field UIFREMAP
|
|
-- in F412,F413 TIM6,7 CNT have field UIFCPY
|
|
|
|
-- Differences between timers
|
|
-- ACT GPT
|
|
-- 1,8 2-5
|
|
-- Count direction Any Any
|
|
-- Slave encoder mode + +
|
|
-- External trigger + +
|
|
-- COM interrupt/DMA + -
|
|
-- Break interrupt + -
|
|
|
|
end STM32.Timers;
|