freebsd-ports/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in

--- riscv/riscv.mk.in.orig	2018-10-05 10:52:11 UTC
+++ riscv/riscv.mk.in
@@ -23,7 +23,7 @@ riscv_hdrs = \
 	tracer.h \
 	extension.h \
 	rocc.h \
-	insn_template.h \
+	insn_template.hpp \
 	mulhi.h \
 	debug_module.h \
 	debug_rom_defines.h \
@@ -31,7 +31,7 @@ riscv_hdrs = \
 	jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
-	insn_template.h \
+	insn_template.hpp \
 
 riscv_srcs = \
 	processor.cc \
- Update to 20181005 snapshot Sponsored by: The FreeBSD Foundation 2018-10-05 13:07:12 +02:00			`--- riscv/riscv.mk.in.orig 2018-10-05 10:52:11 UTC`
			`+++ riscv/riscv.mk.in`
			`@@ -23,7 +23,7 @@ riscv_hdrs = \`
Add RISC-V ISA Simulator: - emulators/riscv-fesvr, RISC-V Frontend Server - emulators/riscv-isa-sim, Spike, a RISC-V ISA Simulator Original work is done by sbruno Reviewed by: br (earlier version) Differential Revision: https://reviews.freebsd.org/D7527 2017-02-07 16:33:04 +01:00			`tracer.h \`
			`extension.h \`
			`rocc.h \`
			`- insn_template.h \`
			`+ insn_template.hpp \`
			`mulhi.h \`
			`debug_module.h \`
- Update to 20181005 snapshot Sponsored by: The FreeBSD Foundation 2018-10-05 13:07:12 +02:00			`debug_rom_defines.h \`
			`@@ -31,7 +31,7 @@ riscv_hdrs = \`
- Update to 20170809 snapshot 2017-08-11 19:50:49 +02:00			`jtag_dtm.h \`
Add RISC-V ISA Simulator: - emulators/riscv-fesvr, RISC-V Frontend Server - emulators/riscv-isa-sim, Spike, a RISC-V ISA Simulator Original work is done by sbruno Reviewed by: br (earlier version) Differential Revision: https://reviews.freebsd.org/D7527 2017-02-07 16:33:04 +01:00
			`riscv_precompiled_hdrs = \`
			`- insn_template.h \`
			`+ insn_template.hpp \`

			`riscv_srcs = \`
			`processor.cc \`