Commit graph

13 commits

Author SHA1 Message Date
Stanislav Sedov
333aa58d8a - Update to 0.8.4. 2007-04-03 23:00:42 +00:00
Stanislav Sedov
6538ef1938 - Update to 0.8.3 2006-11-01 23:28:09 +00:00
Stanislav Sedov
dc494c17e3 - Update to 0.8.2
- Fix compiling with gcc 4.1
- Change my email

Approved by:	sem (mentor)
2006-10-03 13:34:22 +00:00
Marcus Alves Grando
371f431d81 Update to 0.8.1
Add second MASTER_SITES
Add SHA256

PR:		88749
Submitted by:	Joachim Strombergson <watchman@ludd.ltu.se> (maintainer)
2005-11-09 21:36:06 +00:00
Tilman Keskinoz
b84151b7e4 Update to 0.8
PR:		72949
Submitted by:	Joachim Strombergson <watchman@ludd.ltu.se>
2004-11-05 13:16:52 +00:00
MANTANI Nobutaka
8e22e0d446 Update to 0.7.20040606.
PR:		ports/68643
Submitted by:	maintainer
2004-07-04 15:53:09 +00:00
Kirill Ponomarev
a0d455de93 - Update to version 20040220
PR:		ports/64432
Submitted by:	maintainer
2004-03-18 22:19:00 +00:00
Mark Linimon
4805bf3d84 Update to 20031202 snapshot. Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt:

Combination 64bit/32bit runtime support now works fully on AMD64
systems; wait on lists of named events now works; there is no
longer a common iverilog.conf, instead there are target specific
foo.conf files with a new and cleaner format; 64bit values are more
portably handled; several synthesis bugs related to the control inputs
of flip-flops have been fixed.

Committer is marking this BROKEN on 4.x while we investigate install
problems.  It works on 5.x only for now.

PR:		ports/60162
Submitted by:	Joachim Strombergson <watchman@ludd.luth.se> (maintainer)
2003-12-17 16:02:50 +00:00
Mark Linimon
09752ef262 Maintainer Update to latest snapshot. Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320
2003-10-27 10:02:34 +00:00
Mark Linimon
bb01be3ddb Maintainer update to snapshot version. In addition to fixing the port
for gcc3.3, 10 months of updates are included:

- Rework expression parsing and elaboration to accomodate real/realtime
values and expressions.
- Calculate delay statement delays using elaborated expressions instead
of pre-elaborated expression trees.
- Implement the wait statement behaviorally instead of as nets.
- Support event names as expression elements.
- Fix configuration errors, spelling errors, clarification of certain
objects.

See internal revision logs in each file for more elaboration.
2003-10-17 08:26:42 +00:00
Michael C . Wu
01c6cdf8b1 Update to iverilog 0.7
Submitted by:	 Joachim Str?mbergson <watchman@ludd.luth.se>
2003-01-31 17:49:45 +00:00
Michael C . Wu
74d5524ae6 Update to 0.6 after my long absence
PR:		35317
Submitted by:	Joachim Strömbergson <watchman@ludd.luth.se>
2002-03-04 00:46:10 +00:00
Ying-Chieh Liao
7bf8e1d6ec add iverilog, a Verilog simulation and synthesis tool 2001-02-13 11:02:15 +00:00