kpriv/pkgsrc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
pkgsrc/cad/verilog-current/PLIST

30 lines
553 B
Text
Raw Normal View History

Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* *) attributes. * Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes.
2006-08-11 15:28:08 +02:00
@comment $NetBSD: PLIST,v 1.9 2006/08/11 13:28:08 dmcmahill Exp $
Update to verilog-current to the 20000428 snapshot. The many bug fixes and changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog 20000428 Snapshot -------------------------------- This one clears up some pretty nasty and subtle bugs. If you've been sending me bug reports, you're probably turning blue holding your breath in anticipation of this snapshot. Breath in, Breath out. Hooray, both force and release work properly. I'm happy about that, release worked out a bit easier then I expected. These should be useful to test bench designers. The big news this past week, however, has been bug fixes. Lots of bug fixes. I got lots of bug reports and I killed pretty nearly all of them. There were lots of nasty icky problems with passing parameters to/from tasks, especially when memory words were involved. I fixed up a whole bunch of these, and now parameter passing should work pretty will, modulus the few remaining bugs I'm not seeing yet. The iverilog command is in better shape now, and I encourage people to use it in place of the older "verilog" driver script. There is a man page for iverilog, and it supports all the switches needed to do simulation and synthesis. I would like people to start getting this driver well tested and the bugs worked out, because it is going to be the main driver come the next stable release. Some neat new XNF features are happening. I synthesize identity compare in XNF, and a few other missing operators. But the really neato part is that I've taught Icarus Verilog to generate PIN records for module ports, so that you can make XNF macros out of Verilog source. If you elaborate a module that has ports, the XNF code generator will automatically generate the necessary symbols so that external XNF tools can link the generated output into larger designs. I've compared the XNF files from Icarus Verilog with those generated by Abel, and they appear the same to my eyes. Icarus Verilog 20000421 Snapshot -------------------------------- Bunches of bug fixes, and a few new features come with this snapshot. This snapshot makes headway in both simulation and synthesis. I'm also starting to make a big dent in my todo list for the 0.3 release. The bunches of little bug fixes in this snapshot are a direct result of bunches of bug reports this past week that I was able to deal with. If you've been reporting bugs, this may contain your fix. I redesigned the process implementation in the vvm backend, so the generated code is a bit cleaner, and threads are lighter weight. And while I was at it, fork/join now should work properly. I know there were a bunch of you out there asking for this, so here it is. I've incorporated into this release improved runtime support for integer multiplication, it should now work now matter how incredibly enormous you make the operands. Thanks to Chris Lattner for contributing the generic multiply. I've improved synthesis somewhat, there were some expressions in some contexts that were not getting synthesized by the -Fsynth functor. This is fixed, and I'm also starting to add some XNF specific optimizations into the -Fxnfio functor. I do sensible things with identity compare, for example. I've added the program ``iverilog'' to be a new driver program written in C instead of as a shell script. This driver supports the -tnull, -txnf and -tvvm targets, as well as the -E flag that causes only the preprocessor to be run. This should be interesting to those of you who are looking for a working preprocessor. I'm still working on the -D and the -I flags, but I expect this program to replace the verilog.sh script before the 0.3 release. Icarus Verilog 20000414 Snapshot -------------------------------- All event handling is now complete. Yet another subject is behind me, and on I go. By complete, I mean that named events, edge triggers, wait, and lists of events all work. This took a little longer then I expected, so some of the other things I wanted to work on had to wait. As a side effect of event and thread scheduling work, I changed the way that threads are generated in vvm. The result is that threads should be a little faster at run time, and a lot faster at compile time. A *LOT* faster at compile time. (Apparently, Verilog XL is still considerably faster, but hey, I'm working on it.)
2000-04-30 20:15:17 +02:00
bin/iverilog
update to verilog-current-20020505 many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles
2002-05-07 02:11:20 +02:00
bin/iverilog-vpi
update to verilog-current-20010324. Changes since the last version from the authors announcement are: There are a few bugs in the main compiler that are fixed. There has also been an extension to the $fopen that adds support for opening files for reading. The $fgetc has been added to take advantage of this. This was done on the VPI side, although a slight extension to the mcd functions was created. The real news is the vvp simulation engine. I've added the tgt-vvp code generator source and the vvp assembler/simulator, and the combination actually produces the occasional working program. And it makes them very quickly. So far as I can tell now, I am going to be very pleased with the final outcome when this work is complete. However, it is not at all ready to use. This snapshot is mostly to give a preview of things to come to a wider audience. HOW VVP WORKS If you are accustomed to the existing vvm behavior, you remember that the vvm simulator works by generating C++ and feeding that to the g++ compiler. Many of you are painfully aware of that. VVP does *not* work like that. Instead of generating C++, the generator emits assembly language for an abstract simulator processor. The processor that the assembly targets doesn't really exist, but the vvp program, included in this Icarus Verilog snapshot, assembles the code to data structures in memory, then efficiently emulates the abstract processor. So the simulation of a program via vvp works by first compiling the Verilog to vvp assembly. The vvp.tgt modules generates the code, and is envoked when you use the ``-tvvp'' switch to iverilog. The vvp assembly file so created is then passed to the vvp program to be assembled and executed. There is a single vvp input file that is the design to simulate. The vvp assembler is designed to execute the design efficiently. HOW TO LEARN MORE The ivl_target.h header file describes the loadable target API that the vvp code generator uses to gain access to the design. Then the tgt-vvp directory contains the implementation of the vvp code generator. The vvp directory contains the implementation of the assembler/simulator that runs the compiled design. The README.txt file describes how the vvp program works in general, and points to other txt files. There are a variety of other .txt files in the vvp directory that describe how the major components of the vvp program work.
2001-03-31 02:00:35 +02:00
bin/vvp
update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added.
2003-07-14 11:51:48 +02:00
include/_pli_types.h
update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
2002-08-24 06:36:44 +02:00
include/acc_user.h
update to 20001021 snapshot of verilog-current from the authors announcement: ----------------------------- The loadable target module API is starting to take shape. That is the major thrust nowadays with Icarus Verilog, after all, so progress is being made here. The biggest change is in fact a philosophy change. The target module now needs only a single symbol -- target_design -- to receive the whole design. The target module can from there and using the API access the entire design randomly. So if you wanted to implement a graphical browser, you could:-) I've added support for the l-values of procedural assignments, and also back pointers to objects that reference ivl_nexus_t objects. This closes the loop so that there should be no dead-ends in the design. I've clarified and expanded the descriptions in the ivl_target.h header file. There should be just about enough documentation to properly used all the various types. (Have any of you tried to write GIMP plug-ins? Have you looked at the libgimp header files? Have you seen any comments there?-( I won't ever sink to that level, I hope.) I've also imtegrated updates to the Cygwin32 port to support loadable targets under Cygwin32. After much struggling, Venkat managed to discover the secret magic needed to get load time symbol binding to work. Hopefully I didn't break it too bad when I changed the API again. (I think it is still fine.)
2000-10-27 05:59:47 +02:00
include/ivl_target.h
update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
2002-08-24 06:36:44 +02:00
include/veriuser.h
Initial import of verilog-current. This pkg is for the development snapshots of the cad/verilog package. Development snapshots are created quite frequently in between stable releases.
2000-03-07 17:09:15 +01:00
include/vpi_user.h
update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
2002-08-24 06:36:44 +02:00
lib/libveriuser.a
update to 20010630 snapshot. changes are: ----------- RELEASE NOTE FOR ICARUS VERILOG 20010630 I've done some cleanup of the mingw port of Icarus Verilog. I've also added instructions for how to build Icarus Verilog under mingw. I'm working on making that the preferred way to support Windows, and when I make the 0.5 release I will make Windows binaries this way. Anyhow, feedback on the build instructions and the build results using the instructions in mingw.txt are welcome. I've make "vvp" the default target type. The older vvm behavior is available with the "-tvvm" flag to iverilog, but I would rather be told about (and fix) bugs in the vvp code generator and run time. I've added support for the (unsigned) right shift operator. The left shift has been working for a while now, but right shift somehow slipped through the cracks. The shift operators still don't quite work in structural contexts, but they should show up sometime next week. I've finally got VCD output working properly with vvp. It may even be better then with vvm, although some internal symbols are still generated. A few odd bugs have been fixed, including a code generation error for xnf, and error checking of user defined function parameters.
2001-07-03 20:23:46 +02:00
lib/libvpi.a
update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added.
2003-07-14 11:51:48 +02:00
lib/ivl/cadpli.vpl
Initial import of verilog-current. This pkg is for the development snapshots of the cad/verilog package. Development snapshots are created quite frequently in between stable releases.
2000-03-07 17:09:15 +01:00
lib/ivl/ivl
lib/ivl/ivlpp
update to the 20040220 snapshot changes: bugfixes, VPI extensions
2004-03-02 16:34:07 +01:00
lib/ivl/null-s.conf
lib/ivl/null.conf
update verilog-current to 20001216. Changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog snapshot 20001216 -------------------------------- This is the last snapshot before the holidays, so I hope it has your favorite present in it. A lot of PR#s have been dealt with, and for a brief moment I felt like I was getting ahead of the pending list:-) I've added support for non-integer times, at least in a few contexts. The `timescale directives should interact properly with the decimal point in delays, causing more accurate timing simulations. This should make vendor-supplied libraries work much better. I've added support for signed reg variables. Signed expressions should now generally do the right thing, but this feature needs much more testing, and many more tests in the test suite. However, I do know that signed comparisons should work properly. Bug reports for problems with signed arithmetic are encouraged. Many people have been having troubles with Cygwin compilation. The problem was with the latest version of binutils. Venkat came up with a solution that works with old and new binutils, so you can now compile with the very latest cygwin software. This should make things a lot easier for a lot of people. I've made initial steps toward an HP/UX port. The configure script should detect the right dl library to use, and the t-dll target should be able to load loadable targets. I am looking for a volunteer to take responsibility for the HP/UX port as I have no suitable machines. Said person should be able to compile Icarus Verilog, manage HP/UX specific portability issues, and be able to make precompiled packages when the stable release is out. I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}. Some more progress was made on support for PALs. I'm close to choosing macrocell modes and configuring fuses. Won't be long now, folks. Icarus Verilog snapshot 20001129 -------------------------------- few more constant propagation improvements this time, most notably XOR an XNOR are now fairly complete. These are interesting as they are generated by comparison operators so show up pretty often. And it is common to compare numbers to constants. Thus, there are lots of oppor- tunities for gate elimination! Synthesis of unary ! now works. Unary ~| (reduction nor) should also be in good shape now, as should binary || (logical or). Synthesis of binary && is still a little shaky. Go ahead and file reports if you trip on it. Binary != was broken with XNF synthesis, so that is also fixed, along with a few cases of mangled XNF output. And there were also a few bugs related to the CE of inferred DFFs, that didn't get connected. A *big* problem with synthesis occurred with non-blocking assignment. Icarus Verilog simply failed to synthesize the r-value of the assignment and all kinds of bad things happened. I fixed this, it's better now. Whew! Lots of XNF synthesis bugs fixed! This is what happens when users take the time to submit good bug reports. There are also some bugs related to dead signal elimination that causes Icarus Verilog to crash in some synthesis cases. These have been fixed up so far as I know. I have slightly improved root module detection of iverilog. If there is only one module in a source file, it is pretty obvious that it is the root module, even if it has ports. This is a common case for XNF synthesis (especially when making small macros with Icarus Verilog) and should save some typing and confusion.
2000-12-19 19:53:51 +01:00
lib/ivl/null.tgt
Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* *) attributes. * Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes.
2006-08-11 15:28:08 +02:00
lib/ivl/stub-s.conf
lib/ivl/stub.conf
lib/ivl/stub.tgt
update to verilog-current-20040828 changes include: Added support for the `default_nettype directine, including the default net type of "none", which turns off implicit net declarations. Signed /, % and >>> in nets should now work properly. Also, various operators of all sorts applied to constants have been improved. Ranges now work on localparams. Added the system tasks $unsigned, $is_signed, $mti_random and $mti-dist_uniform. See the make README.txt for a description of these system functions. Also, flesh out the standard random number generators to match the sequences generated by other compilers. There is now an "sft" file that describes to the compiler the return value of system functions. This allows user supplied system functions to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in the iverilog man page. Include a sft file for the system functions, and move the system functions over to that mechinism. Fix the behavior of $fgets in tight fitting result buffers. A variety of compilation environment fixes have been added. These involve configure scripts and Makefiles. And of course a variety of other bug fixes, and so on and so forth.
2004-09-02 03:55:47 +02:00
lib/ivl/system.sft
Update to verilog-current-20000318. Notable changes since the last pkg are (from the snapshot announcement): Parameters are complete. What this means is that I finally got around to supporting defparam, and while I was at it I rewrote the entire parameter handling and added the parameter support included in 1364-2000. I have rewritten major portions of the VVM backend. The vvm_nexus class has been introduced to the fray, and all the device implementations in the VVM library now use the nexus to drive and receive values. An advantage of this scheme is that the t-vvm backend code (in ivl proper) is simpler, and so is the generated C++ code. I also removed most of the template classes. This proved to be a huge compile-time benefit (though compiling twice as fast really only matters for large programs) and it doesn't seem likely to hurt run-time performance. A few remain, either because they seemed harmless (the N-wide logic gates) or I couldn't yet figure out a good way to replace them (vvm_bitset_t). A side benefit of this is that the vvm library may now be a modeling library that ordinary humans can use to write their models in C++. This may provide the unexpected benefit of heading me towards incremental compilation of designs. So who was it who was beating me over the head asking for that?-) I also fixed a few minor problems with the preprocessor. Those of you who reported problems with `includes and `defines should check this out.
2000-03-25 22:09:16 +01:00
lib/ivl/system.vpi
update to the 20040220 snapshot changes: bugfixes, VPI extensions
2004-03-02 16:34:07 +01:00
lib/ivl/vvp-s.conf
lib/ivl/vvp.conf
update to verilog-current-20010324. Changes since the last version from the authors announcement are: There are a few bugs in the main compiler that are fixed. There has also been an extension to the $fopen that adds support for opening files for reading. The $fgetc has been added to take advantage of this. This was done on the VPI side, although a slight extension to the mcd functions was created. The real news is the vvp simulation engine. I've added the tgt-vvp code generator source and the vvp assembler/simulator, and the combination actually produces the occasional working program. And it makes them very quickly. So far as I can tell now, I am going to be very pleased with the final outcome when this work is complete. However, it is not at all ready to use. This snapshot is mostly to give a preview of things to come to a wider audience. HOW VVP WORKS If you are accustomed to the existing vvm behavior, you remember that the vvm simulator works by generating C++ and feeding that to the g++ compiler. Many of you are painfully aware of that. VVP does *not* work like that. Instead of generating C++, the generator emits assembly language for an abstract simulator processor. The processor that the assembly targets doesn't really exist, but the vvp program, included in this Icarus Verilog snapshot, assembles the code to data structures in memory, then efficiently emulates the abstract processor. So the simulation of a program via vvp works by first compiling the Verilog to vvp assembly. The vvp.tgt modules generates the code, and is envoked when you use the ``-tvvp'' switch to iverilog. The vvp assembly file so created is then passed to the vvp program to be assembled and executed. There is a single vvp input file that is the design to simulate. The vvp assembler is designed to execute the design efficiently. HOW TO LEARN MORE The ivl_target.h header file describes the loadable target API that the vvp code generator uses to gain access to the design. Then the tgt-vvp directory contains the implementation of the vvp code generator. The vvp directory contains the implementation of the assembler/simulator that runs the compiled design. The README.txt file describes how the vvp program works in general, and points to other txt files. There are a variety of other .txt files in the vvp directory that describe how the major components of the vvp program work.
2001-03-31 02:00:35 +02:00
lib/ivl/vvp.tgt
Update to verilog-current to the 20000428 snapshot. The many bug fixes and changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog 20000428 Snapshot -------------------------------- This one clears up some pretty nasty and subtle bugs. If you've been sending me bug reports, you're probably turning blue holding your breath in anticipation of this snapshot. Breath in, Breath out. Hooray, both force and release work properly. I'm happy about that, release worked out a bit easier then I expected. These should be useful to test bench designers. The big news this past week, however, has been bug fixes. Lots of bug fixes. I got lots of bug reports and I killed pretty nearly all of them. There were lots of nasty icky problems with passing parameters to/from tasks, especially when memory words were involved. I fixed up a whole bunch of these, and now parameter passing should work pretty will, modulus the few remaining bugs I'm not seeing yet. The iverilog command is in better shape now, and I encourage people to use it in place of the older "verilog" driver script. There is a man page for iverilog, and it supports all the switches needed to do simulation and synthesis. I would like people to start getting this driver well tested and the bugs worked out, because it is going to be the main driver come the next stable release. Some neat new XNF features are happening. I synthesize identity compare in XNF, and a few other missing operators. But the really neato part is that I've taught Icarus Verilog to generate PIN records for module ports, so that you can make XNF macros out of Verilog source. If you elaborate a module that has ports, the XNF code generator will automatically generate the necessary symbols so that external XNF tools can link the generated output into larger designs. I've compared the XNF files from Icarus Verilog with those generated by Abel, and they appear the same to my eyes. Icarus Verilog 20000421 Snapshot -------------------------------- Bunches of bug fixes, and a few new features come with this snapshot. This snapshot makes headway in both simulation and synthesis. I'm also starting to make a big dent in my todo list for the 0.3 release. The bunches of little bug fixes in this snapshot are a direct result of bunches of bug reports this past week that I was able to deal with. If you've been reporting bugs, this may contain your fix. I redesigned the process implementation in the vvm backend, so the generated code is a bit cleaner, and threads are lighter weight. And while I was at it, fork/join now should work properly. I know there were a bunch of you out there asking for this, so here it is. I've incorporated into this release improved runtime support for integer multiplication, it should now work now matter how incredibly enormous you make the operands. Thanks to Chris Lattner for contributing the generic multiply. I've improved synthesis somewhat, there were some expressions in some contexts that were not getting synthesized by the -Fsynth functor. This is fixed, and I'm also starting to add some XNF specific optimizations into the -Fxnfio functor. I do sensible things with identity compare, for example. I've added the program ``iverilog'' to be a new driver program written in C instead of as a shell script. This driver supports the -tnull, -txnf and -tvvm targets, as well as the -E flag that causes only the preprocessor to be run. This should be interesting to those of you who are looking for a working preprocessor. I'm still working on the -D and the -I flags, but I expect this program to replace the verilog.sh script before the 0.3 release. Icarus Verilog 20000414 Snapshot -------------------------------- All event handling is now complete. Yet another subject is behind me, and on I go. By complete, I mean that named events, edge triggers, wait, and lists of events all work. This took a little longer then I expected, so some of the other things I wanted to work on had to wait. As a side effect of event and thread scheduling work, I changed the way that threads are generated in vvm. The result is that threads should be a little faster at run time, and a lot faster at compile time. A *LOT* faster at compile time. (Apparently, Verilog XL is still considerably faster, but hey, I'm working on it.)
2000-04-30 20:15:17 +02:00
man/man1/iverilog.1
update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
2002-08-24 06:36:44 +02:00
man/man1/iverilog-vpi.1
update to verilog-current-20011020. changes since last snapshot include: - addition of a fpga target for synthesis. outputs edif, optimized for xilinx virtex parts. - fixed bug with synthesis of != - fixed bug in hex constant parsing - fixed vvp bug with subtracting very wide words - much improved VCD output - many other bug fixes and robustness improvements.
2001-10-24 14:27:11 +02:00
man/man1/vvp.1
Initial import of verilog-current. This pkg is for the development snapshots of the cad/verilog package. Development snapshots are created quite frequently in between stable releases.
2000-03-07 17:09:15 +01:00
@dirrm lib/ivl
Reference in a new issue Copy permalink