ceef8b004b
-------------------------- Release notes for EAGLE 7.7.0 ============================= * Licensing: - Update of various spots in EAGLE regarding the license changes introduced by Autodesk: Standard, Premium, Ultimate, Express and Educational. The 30 day trial license has been removed. * ULPs: - Added 'manufacturing.ulp' provided by Autodesk. It supports an upload of EAGLE drawing files to 'circuits.io' in order to generate manufacturing data which can then be downloaded. The ULP is accessible as an icon in the board editor. - Added 'ecadio.ulp' provided by Autodesk. It supports an upload of EAGLE boards to 'ecad.io' in order to generate a 3D PCB for use in MCAD systems. The ULP is accessible as an icon in the board editor. * UI improvements: - Added Option.SignalNames to display the signal names on the signal wires and on the connected pads and SMDs. It can be set in the Settings dialog under 'Misc/Display signal names'. - The options Option.SignalNames, Option.PadNames and Option.ViaLength are set to 'On' by default. * Miscellaneous: - Improved visibility of scrollbars for common window styles on Linux. - Silently ignoring double references to a contact within a signal when loading a board file. - CAM Processor: when running 'Process Job' with more than one section, it is checked if the job covers the Layer Setup only partially. - The file locking option has been switched off by default. Use 'Backup/Locking' under 'Options' in Control Panel to turn it on. - Update of EAGLE logo to the new appearance since Autodesk acquisition. - Update of Hungarian translation (GUI without help and manual). * Bugfixes: - Fixed UL functions strsplit() and lookup() to handle unusual UTF8 characters as separator. - Fixed potential crash of the 64 bit versions when loading EAGLE drawings from old format (e.g. V3.55). - Image export to TIFF format in monochrome: fixed a regression regarding the compression method. - The selected object is no longer removed from the group after running a ULP started through 'SET CONTEXT Object ...'; the ULP might want to use this one-object group afterwards with e.g. 'exit("move (>@)")'. - Ensuring valid move of polygon wires or an entire polygon if selecting a wire with 'SET CONTEXT Wire ...' or using setgroup() in a ULP. - Fixed history of dlgStringEdit to become case sensitive. - Fix for refresh of images in Control Panel preview on Windows. - Added a check for identical pinrefs when loading a schematic to avoid a possible crash. - Fixed deleting/splitting busses with portrefs involved: it could happen that new port connections couldn't be established anymore. - Fixed selecting an end of a wire with the context menu. - Fix for ULP function ingroup() returning true for too many objects after UNDOing of transferring a group to another sheet. |
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adms | ||
atlc | ||
boolean | ||
cascade | ||
cgi-wcalc | ||
covered | ||
dinotrace | ||
dinotrace-mode | ||
diylc | ||
eagle | ||
electric | ||
fastcap | ||
fasthenry | ||
felt | ||
freehdl | ||
gdsreader | ||
geda | ||
gerbv | ||
ghdl | ||
gnetman | ||
gnucap | ||
gplcver | ||
gsmc | ||
gtk1-wcalc | ||
gtk2-wcalc | ||
gtkwave | ||
iverilog | ||
kicad | ||
kicad-doc | ||
kicad-footprints | ||
kicad-i18n | ||
kicad-lib | ||
klayout | ||
librecad | ||
libwcalc | ||
magic | ||
mcalc | ||
mex-wcalc | ||
mpac | ||
MyHDL-gplcver | ||
MyHDL-iverilog | ||
nelma | ||
ng-spice | ||
ntesla | ||
openscad | ||
p5-gds2 | ||
pcb | ||
py-gds | ||
py-MyHDL | ||
py-simpy | ||
qcad | ||
qcad-partlibrary | ||
sci-wcalc | ||
spice | ||
spiceprm | ||
stdio-wcalc | ||
tkgate | ||
tnt-mmtl | ||
transcalc | ||
verilog-mode | ||
veriwell | ||
vipec | ||
wcalc | ||
wcalc-docs | ||
xchiplogo | ||
xcircuit | ||
Makefile |