7f78417fed
CGEN (pronounced seejen) is a framework for developing generators of CPU-related tools such as assemblers, disassemblers and simulators. It specifies a description language for describing the architecture and organization of a CPU without reference to any particular application. Additional applications can be written within the framework. CGEN is written in Scheme and can be run under the GNU Guile interpreter. It is placed under a free software license.
189 lines
5.4 KiB
Text
189 lines
5.4 KiB
Text
@comment $NetBSD: PLIST,v 1.1 2013/10/12 08:39:02 ryoon Exp $
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info/cgen.info
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info/cgenint.info
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share/cgen/cgen/AUTHORS
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share/cgen/cgen/COPYING.CGEN
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share/cgen/cgen/ChangeLog
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share/cgen/cgen/INSTALL
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share/cgen/cgen/Makefile.am
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share/cgen/cgen/Makefile.in
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share/cgen/cgen/NEWS
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share/cgen/cgen/README
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share/cgen/cgen/aclocal.m4
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share/cgen/cgen/attr.scm
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share/cgen/cgen/cgen-doc.scm
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share/cgen/cgen/cgen-gas.scm
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share/cgen/cgen/cgen-intrinsics.scm
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share/cgen/cgen/cgen-opc.scm
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share/cgen/cgen/cgen-sid.scm
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share/cgen/cgen/cgen-sim.scm
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share/cgen/cgen/cgen-stest.scm
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share/cgen/cgen/cgen-testsuite.scm
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share/cgen/cgen/co-for-gen-all
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share/cgen/cgen/cos-pprint.scm
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share/cgen/cgen/cos.scm
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share/cgen/cgen/cpu/arm.cpu
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share/cgen/cgen/cpu/arm.sim
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share/cgen/cgen/cpu/arm7.cpu
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share/cgen/cgen/cpu/i960.cpu
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share/cgen/cgen/cpu/i960.opc
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share/cgen/cgen/cpu/ia32.cpu
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share/cgen/cgen/cpu/ia64.cpu
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share/cgen/cgen/cpu/m68k.cpu
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share/cgen/cgen/cpu/play.cpu
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share/cgen/cgen/cpu/play.opc
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share/cgen/cgen/cpu/powerpc.cpu
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share/cgen/cgen/cpu/sh-sid.cpu
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share/cgen/cgen/cpu/sh-sim.cpu
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share/cgen/cgen/cpu/sh.cpu
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share/cgen/cgen/cpu/sh.opc
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share/cgen/cgen/cpu/sh64-compact.cpu
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share/cgen/cgen/cpu/sh64-media.cpu
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share/cgen/cgen/cpu/simplify.inc
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share/cgen/cgen/cpu/sparc.cpu
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share/cgen/cgen/cpu/sparc.opc
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share/cgen/cgen/cpu/sparc32.cpu
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share/cgen/cgen/cpu/sparc64.cpu
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share/cgen/cgen/cpu/sparccom.cpu
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share/cgen/cgen/cpu/sparcfpu.cpu
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share/cgen/cgen/cpu/thumb.cpu
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share/cgen/cgen/decode.scm
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share/cgen/cgen/desc-cpu.scm
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share/cgen/cgen/desc.scm
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share/cgen/cgen/dev-utils.scm
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share/cgen/cgen/dev.scm
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share/cgen/cgen/doc/Makefile.am
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share/cgen/cgen/doc/Makefile.in
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share/cgen/cgen/doc/app.texi
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share/cgen/cgen/doc/cgen.info
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share/cgen/cgen/doc/cgen.texi
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share/cgen/cgen/doc/cgenint.info
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share/cgen/cgen/doc/cgenint.texi
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share/cgen/cgen/doc/credits.texi
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share/cgen/cgen/doc/glossary.texi
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share/cgen/cgen/doc/intro.texi
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share/cgen/cgen/doc/mdate-sh
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share/cgen/cgen/doc/notes.texi
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share/cgen/cgen/doc/opcodes.texi
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share/cgen/cgen/doc/pmacros.texi
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share/cgen/cgen/doc/porting.texi
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share/cgen/cgen/doc/rtl.texi
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share/cgen/cgen/doc/running.texi
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share/cgen/cgen/doc/sim.texi
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share/cgen/cgen/doc/stamp-vti
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share/cgen/cgen/doc/version.texi
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share/cgen/cgen/enum.scm
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share/cgen/cgen/gas-test.scm
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share/cgen/cgen/gen-all
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share/cgen/cgen/gen-all-desc
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share/cgen/cgen/gen-all-doc
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share/cgen/cgen/gen-all-intrinsics
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share/cgen/cgen/gen-all-opcodes
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share/cgen/cgen/gen-all-sid
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share/cgen/cgen/gen-all-sim
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share/cgen/cgen/guile.scm
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share/cgen/cgen/hardware.scm
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share/cgen/cgen/html.scm
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share/cgen/cgen/ifield.scm
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share/cgen/cgen/iformat.scm
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share/cgen/cgen/insn.scm
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share/cgen/cgen/intrinsics.scm
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share/cgen/cgen/mach.scm
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share/cgen/cgen/minsn.scm
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share/cgen/cgen/mode.scm
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share/cgen/cgen/model.scm
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share/cgen/cgen/opc-asmdis.scm
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share/cgen/cgen/opc-ibld.scm
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share/cgen/cgen/opc-itab.scm
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share/cgen/cgen/opc-opinst.scm
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share/cgen/cgen/opcodes.scm
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share/cgen/cgen/operand.scm
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share/cgen/cgen/pgmr-tools.scm
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share/cgen/cgen/pmacros.scm
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share/cgen/cgen/pprint.scm
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share/cgen/cgen/profile.scm
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share/cgen/cgen/read.scm
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share/cgen/cgen/rtl-c.scm
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share/cgen/cgen/rtl-traverse.scm
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share/cgen/cgen/rtl-xform.scm
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share/cgen/cgen/rtl.scm
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share/cgen/cgen/rtx-funcs.scm
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share/cgen/cgen/sem-frags.scm
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share/cgen/cgen/semantics.scm
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share/cgen/cgen/sid-cpu.scm
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share/cgen/cgen/sid-decode.scm
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share/cgen/cgen/sid-model.scm
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share/cgen/cgen/sid.scm
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share/cgen/cgen/sim-arch.scm
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share/cgen/cgen/sim-cpu.scm
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share/cgen/cgen/sim-decode.scm
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share/cgen/cgen/sim-model.scm
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share/cgen/cgen/sim-test.scm
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share/cgen/cgen/sim.scm
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share/cgen/cgen/slib/genwrite.scm
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share/cgen/cgen/slib/logical.scm
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share/cgen/cgen/slib/pp.scm
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share/cgen/cgen/slib/random.scm
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share/cgen/cgen/slib/sort.scm
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share/cgen/cgen/stamp-h.in
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share/cgen/cgen/testsuite.scm
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share/cgen/cgen/testsuite/Makefile.am
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share/cgen/cgen/testsuite/Makefile.in
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share/cgen/cgen/testsuite/location-1.test
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share/cgen/cgen/testsuite/names-comments-1.test
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share/cgen/cgen/testsuite/pmacros-1.test
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share/cgen/cgen/testsuite/run-tests.sh
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share/cgen/cgen/testsuite/test-utils.sh
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share/cgen/cgen/testsuite/test-utils.sh.in
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share/cgen/cgen/testsuite/testsuite.cpu
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share/cgen/cgen/types.scm
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share/cgen/cgen/utils-cgen.scm
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share/cgen/cgen/utils-gen.scm
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share/cgen/cgen/utils-sim.scm
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share/cgen/cgen/utils.scm
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share/cgen/cpu/ChangeLog
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share/cgen/cpu/cris.cpu
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share/cgen/cpu/epiphany.cpu
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share/cgen/cpu/epiphany.opc
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share/cgen/cpu/fr30.cpu
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share/cgen/cpu/fr30.opc
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share/cgen/cpu/frv.cpu
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share/cgen/cpu/frv.opc
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share/cgen/cpu/ip2k.cpu
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share/cgen/cpu/ip2k.opc
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share/cgen/cpu/iq10.cpu
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share/cgen/cpu/iq2000.cpu
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share/cgen/cpu/iq2000.opc
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share/cgen/cpu/iq2000m.cpu
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share/cgen/cpu/lm32.cpu
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share/cgen/cpu/lm32.opc
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share/cgen/cpu/m32c.cpu
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share/cgen/cpu/m32c.opc
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share/cgen/cpu/m32r.cpu
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share/cgen/cpu/m32r.opc
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share/cgen/cpu/mep-avc.cpu
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share/cgen/cpu/mep-avc2.cpu
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share/cgen/cpu/mep-c5.cpu
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share/cgen/cpu/mep-core.cpu
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share/cgen/cpu/mep-default.cpu
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share/cgen/cpu/mep-ext-cop.cpu
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share/cgen/cpu/mep-fmax.cpu
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share/cgen/cpu/mep-h1.cpu
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share/cgen/cpu/mep-ivc2.cpu
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share/cgen/cpu/mep-rhcop.cpu
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share/cgen/cpu/mep-sample-ucidsp.cpu
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share/cgen/cpu/mep.cpu
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share/cgen/cpu/mep.opc
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share/cgen/cpu/mt.cpu
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share/cgen/cpu/mt.opc
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share/cgen/cpu/openrisc.cpu
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share/cgen/cpu/openrisc.opc
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share/cgen/cpu/sh.cpu
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share/cgen/cpu/sh.opc
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share/cgen/cpu/sh64-compact.cpu
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share/cgen/cpu/sh64-media.cpu
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share/cgen/cpu/simplify.inc
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share/cgen/cpu/xc16x.cpu
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share/cgen/cpu/xc16x.opc
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share/cgen/cpu/xstormy16.cpu
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share/cgen/cpu/xstormy16.opc
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