freebsd-ports/cad/Makefile

# $FreeBSD$
#

    COMMENT = CAD tools

    SUBDIR += admesh
    SUBDIR += adms
    SUBDIR += alliance
    SUBDIR += astk-client
    SUBDIR += astk-serveur
    SUBDIR += atlc
    SUBDIR += brlcad
    SUBDIR += calculix
    SUBDIR += cascade
    SUBDIR += chipmunk
    SUBDIR += chipvault
    SUBDIR += cider
    SUBDIR += dinotrace
    SUBDIR += dxf2fig
    SUBDIR += electric
    SUBDIR += electric-ng
    SUBDIR += fandango
    SUBDIR += feappv
    SUBDIR += findhier
    SUBDIR += freehdl
    SUBDIR += gdsreader
    SUBDIR += geda
    SUBDIR += geda-docs
    SUBDIR += geda-examples
    SUBDIR += geda-gattrib
    SUBDIR += geda-gschem
    SUBDIR += geda-netlist
    SUBDIR += geda-symbols
    SUBDIR += geda-symcheck
    SUBDIR += geda-utils
    SUBDIR += gerbv
    SUBDIR += gmsh
    SUBDIR += gnucap
    SUBDIR += gplcver
    SUBDIR += gspiceui
    SUBDIR += gtkwave
    SUBDIR += gwave
    SUBDIR += impact
    SUBDIR += irsim
    SUBDIR += iverilog
    SUBDIR += jspice3
    SUBDIR += kicad
    SUBDIR += klayout
    SUBDIR += leocad
    SUBDIR += libgeda
    SUBDIR += linux-eagle
    SUBDIR += linux-gid
    SUBDIR += magic
    SUBDIR += mars
    SUBDIR += netgen
    SUBDIR += ngspice_rework
    SUBDIR += opencascade
    SUBDIR += opencascade-tutorial
    SUBDIR += oregano
    SUBDIR += p5-GDS2
    SUBDIR += pcb
    SUBDIR += pdnmesh
    SUBDIR += pythoncad
    SUBDIR += qcad
    SUBDIR += qcad-partslib
    SUBDIR += qfsm
    SUBDIR += qmls
    SUBDIR += qucs
    SUBDIR += sceptre
    SUBDIR += scotch
    SUBDIR += scv
    SUBDIR += slffea
    SUBDIR += spice
    SUBDIR += systemc
    SUBDIR += tclspice
    SUBDIR += tkgate
    SUBDIR += tochnog
    SUBDIR += transcalc
    SUBDIR += varkon
    SUBDIR += vipec
    SUBDIR += xcircuit
    SUBDIR += z88

.include <bsd.port.subdir.mk>
Change Id->FreeBSD. 1999-08-25 06:58:03 +02:00			`# $FreeBSD$`
New cad group 1995-01-13 12:10:43 +01:00			`#`
Clean up subdir Makefiles. They now all look like this: ===== # Id line # # RESTRICTED: restricted_port_1 (comment1) # RESTRICTED: restricted_port_2 (comment2) # # BROKEN: broken_port_3 (comment3) # BROKEN: broken_port_4 (comment4) # BROKEN: broken_port_5 (comment5) # SUBDIR= good_port_1 good_port_2 ... ===== Basically, the idea is to make it easy to find restricted or broken ports by doing a "grep". 1995-05-14 05:30:07 +02:00
Remove category pkg/COMMENT files in favour of a COMMENT variable in the category makefile. Submitted by: Matthew Seaman <m.seaman@infracaninophile.co.uk> PR: 59651 2004-04-02 09:29:48 +02:00			`COMMENT = CAD tools`

NEW port CAD/admesh A tool to analyze STL (stereolitholigraphy) files. PR: ports/52997 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> 2003-10-10 07:16:19 +02:00			`SUBDIR += admesh`
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. WWW: http://mot-adms.sourceforge.net/ PR: ports/101014 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru> 2006-07-29 23:10:26 +02:00			`SUBDIR += adms`
Add cad/alliance, which is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, automatic place and route tools, and portable CMOS libraries. Approved by: linimon (mentor) 2004-05-13 20:51:03 +02:00			`SUBDIR += alliance`
Add astk-client , graphical interface for Code_Aster (client side). PR: 54765 Submitted by: thierry@pompo.net 2003-07-23 13:25:42 +02:00			`SUBDIR += astk-client`
Add astk-serveur 1.0.14, graphical interface for Code_Aster (server side). PR: 54764 Submitted by: thierry@pompo.net 2003-07-23 13:20:26 +02:00			`SUBDIR += astk-serveur`
New port atlc version 4.0.1: A tool to calculate the impedance of transmission lines Submitted by: blackend 2002-11-13 21:21:29 +01:00			`SUBDIR += atlc`
Add brlcad 7.0.4, CSG modelling system from the US Balistic Research Laboratory. PR: 76122 Submitted by: Pedro F. Giffuni 2005-02-20 23:00:46 +01:00			`SUBDIR += brlcad`
A Three-Dimensional Structural Finite Element Program Submitted by : Pedro F. Giffuni <giffunip@yahoo.com> Almost writeen by: maho 2003-05-05 15:06:37 +02:00			`SUBDIR += calculix`
New port cascade version 1.4: A simple tool to analyze noise and distortion of a RF system Submitted by: blackend 2002-11-13 20:12:13 +01:00			`SUBDIR += cascade`
Add chipmunk, convert to new format along the way. 1995-08-25 12:06:06 +02:00			`SUBDIR += chipmunk`
add chipvault 200211 A project organizer for VHDL and Verilog RTL hardware designs 2003-01-29 04:45:13 +01:00			`SUBDIR += chipvault`
cider version 1b1 A mixed-level circuit and device simulator (includes SPICE3). PR: 15462 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org> 1999-12-25 16:40:48 +01:00			`SUBDIR += cider`
Add dinotrace, a mature signal waveform viewer used to debug digital design simulations. PR: ports/68688 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se> 2004-07-05 23:02:41 +02:00			`SUBDIR += dinotrace`
add dxf2fig 2.07 DXF to FIG converter 2004-08-26 11:38:31 +02:00			`SUBDIR += dxf2fig`
Activate Electric. PR: ports/18380 Submitted by: Mario Sergio Fujikawa Ferreira <lioux@linf.unb.br> 2000-07-30 09:14:47 +02:00			`SUBDIR += electric`
Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications Author: Static Free Software & Sun Microsystems, Inc. WWW: http://www.staticfreesoft.com/ PR: ports/100355 Submitted by: me (stas) Approved by: sem (mentor) 2006-09-30 11:41:07 +02:00			`SUBDIR += electric-ng`
add fandango 0.2.5 A python scripted 3D CAD application 2004-02-20 02:58:45 +01:00			`SUBDIR += fandango`
Add feappv 2.0, finite Element Analysis Program "personal version". This is a FEA program used in a classic FEM book. A complete (commercial) version is available here: <http://www.ce.berkeley.edu/~rlt/feap/> The "personal version" is very limited, but it keeps the same format as the complete (commercial) version and cad/netgen can produce files for it. PR: ports/95210 Submitted by: Pedro F. Giffuni <giffunip (at) asme.org> 2006-04-03 21:57:24 +02:00			`SUBDIR += feappv`
FindHier is a road-map generator for Magic/CIF/gdsII/PCSTR/GED/TeX. ---When you have a large number of or big layout/schematic/TeX files which have possibly many top cells made by other people, how can you manage those layout/schematic/TeXs? FH is written for that. It can be useful up to your imagination or shell programming skill. FH analyses the hidden hierarchies of those cells and shows you the hierarchy information. 2007-04-28 19:01:15 +02:00			`SUBDIR += findhier`
The goals of the FreeHDL project are to develop a VHDL simulator that has a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage. WWW: http://www.freehdl.seul.org/ PR: ports/104634 Submitted by: lon_kamikaze at gmx.de 2006-11-05 21:51:06 +01:00			`SUBDIR += freehdl`
GDSreader is a simple Calma (GDSii) parser/printer tool. 2007-04-28 18:56:55 +02:00			`SUBDIR += gdsreader`
Activate geda. 1998-12-06 15:13:23 +01:00			`SUBDIR += geda`
Various documentation for gEDA suite, including architecture-related docs as well as examples of usage and tutorials. WWW: http://www.geda.seul.org PR: ports/99565 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> 2006-07-04 17:26:09 +02:00			`SUBDIR += geda-docs`
Various examples for gEDA suite. This includes: 1) gTAG - USB to JTAG interface 2) lightning_detector - a lightning detector 3) RF_Amp - schematics and associated materials for a SPICE model 4) TwoStageAmp - a two stage amplifier SPICE playpen WWW: http://www.geda.seul.org PR: ports/99564 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> 2006-07-04 17:31:24 +02:00			`SUBDIR += geda-examples`
Gattrib is gEDA's attribute editor. WWW: http://www.geda.seul.org PR: ports/99480 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> 2006-06-27 00:09:30 +02:00			`SUBDIR += geda-gattrib`
- gschem -> geda-gschem - gnetlist -> geda-netlist PR: ports/100222, ports/100230 Submitted by: maintainer 2006-07-16 06:00:28 +02:00			`SUBDIR += geda-gschem`
			`SUBDIR += geda-netlist`
geda-symbols is the basic component of geda package. Submitted byu.schwander@technologist.com 2001-04-07 02:17:32 +02:00			`SUBDIR += geda-symbols`
add geda-symcheck gEDA symbol checking utility PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org> 2002-10-10 20:35:25 +02:00			`SUBDIR += geda-symcheck`
add geda-utils gEDA utilities PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org> 2002-10-10 20:38:37 +02:00			`SUBDIR += geda-utils`
add gerbv 0.0.9 A Free Gerber Viewer 2002-07-15 22:00:33 +02:00			`SUBDIR += gerbv`
Add gmsh 1.45.1, an automatic 3D finite element mesh generator. PR: 52201 Submitted by: Pedro Giffuni <giffunip@yahoo.com> 2003-07-23 16:21:51 +02:00			`SUBDIR += gmsh`
add gnucap 0.30 The Gnu Circuit Analysis Package 2002-02-07 08:07:48 +01:00			`SUBDIR += gnucap`
[NEW PORT] cad/gplcver: A Verilog HDL simulator GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw> 2005-12-29 04:48:58 +01:00			`SUBDIR += gplcver`
This port provides a GUI for two freely available SPICE electronic circuit simulation engines: GNU-Cap and Ng-Spice. Current features: Import gschem schematic files using gentlist. Load and parse circuit description (net list) files. Provides a GUI interface for GNU-Cap OP, DC, AC and Transient analyses and generates appropriate simulator commands based on user input. Provides a GUI interface for Ng-Spice DC, AC and Transient analyses and generates appropriate simulator commands based on user input. The raw output may be viewed for any processes initiated by gspiceui. Formatting of simulator output so that it may be plotted using gwave. WWW: http://www.geda.seul.org/tools/gspiceui/index.html PR: ports/99357 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru> 2006-08-01 22:22:11 +02:00			`SUBDIR += gspiceui`
add gtkwave 2.0.0p1 Electronic Waveform Viewer 2002-05-12 17:14:08 +02:00			`SUBDIR += gtkwave`
new port: cad/gwave Gwave is a waveform viewer. Its purpose is for viewing analog data, such as the output from Spice-like simulations. PR: ports/39364 Submitted by: Duncan Barclay <dmlb@dmlb.org> 2003-01-19 01:35:38 +01:00			`SUBDIR += gwave`
add impact 0.5.3 Dynamic Finite Element Program Suite 2005-03-04 08:36:48 +01:00			`SUBDIR += impact`
Add chipmunk, convert to new format along the way. 1995-08-25 12:06:06 +02:00			`SUBDIR += irsim`
add iverilog, a Verilog simulation and synthesis tool 2001-02-13 12:02:15 +01:00			`SUBDIR += iverilog`
Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability. WWW: http://www.wrcad.com/jspice3.html PR: ports/93958 Submitted by: Pedro F. Giffuni Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it. 2006-07-11 21:34:46 +02:00			`SUBDIR += jspice3`
Add Kicad, a software for the creation of electronic schematic diagrams and printed circuit board artwork. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager. 2005-12-09 00:30:13 +01:00			`SUBDIR += kicad`
KLayout is a Qt-based GDS2 viewer. 2007-04-28 20:55:05 +02:00			`SUBDIR += klayout`
Add leocad 0.73, a CAD program that uses bricks similar to those found in many toys. PR: 35231 Submitted by: David Yeske <dyeske@yahoo.com> 2002-03-03 01:40:21 +01:00			`SUBDIR += leocad`
libgeda is a a base library common to all the gEDA tools Submitted by: bruno.schwander@technologist.com 2001-04-07 02:09:57 +02:00			`SUBDIR += libgeda`
Add linux-eagle , an easy to use, yet powerful tool for designing printed circuit boards. 2001-12-26 17:12:17 +01:00			`SUBDIR += linux-eagle`
Add linux-gid 7.4.9b, a graphical pre- and post-processor for numerical simulation programs. PR: ports/78383 Submitted by: Pedro Giffuni Approved by: arved (mentor) 2005-03-16 13:49:07 +01:00			`SUBDIR += linux-gid`
Add chipmunk, convert to new format along the way. 1995-08-25 12:06:06 +02:00			`SUBDIR += magic`
Turn on mars and lprps 1996-11-25 02:24:47 +01:00			`SUBDIR += mars`
Add netgen 4.3.1, an automatic 3D tetrahedral mesh generator. 2004-05-05 21:57:56 +02:00			`SUBDIR += netgen`
Initial import of ngspice_rework Ngspice_rework is a circuit simulator derived from spice3f5. PR: 34589 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org> 2002-02-09 11:03:42 +01:00			`SUBDIR += ngspice_rework`
Open CASCADE Technology is a software development platform freely available in open source. It includes components for 3D surface and solid modeling, visualization, data exchange and rapid application development. Open CASCADE Technology can be best applied in development of numerical simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM applications. BUGS: the module WOK does not work, but the other modules (the most interesting parts) are OK. 2007-04-01 11:04:04 +02:00			`SUBDIR += opencascade`
A Qt based application for tutorial to Open CASCADE Technology. 2007-04-01 11:05:46 +02:00			`SUBDIR += opencascade-tutorial`
Add oregano, schematic capture and simulation of electrical circuits. PR: ports/25202 Submitted by: Anders Andersson <anders@codefactory.se> 2001-03-07 12:00:31 +01:00			`SUBDIR += oregano`
p5-GDS2, a Perl module for quickly creating programs to read and/or write GDS2 files. 2007-04-29 09:17:29 +02:00			`SUBDIR += p5-GDS2`
Add chipmunk, convert to new format along the way. 1995-08-25 12:06:06 +02:00			`SUBDIR += pcb`
add pdnmesh A finite element program PR: 30115 Submitted by: Sarod Yatawatta <sarod@cs.pdn.ac.lk> 2001-10-14 19:54:31 +02:00			`SUBDIR += pdnmesh`
add pythoncad release 10 An open-source CAD package built designed around Python 2003-11-12 03:01:27 +01:00			`SUBDIR += pythoncad`
New port QCad, a 2D-CAD program. Uses Qt-2. 1999-12-22 11:40:56 +01:00			`SUBDIR += qcad`
add qcad-partslib the parts-library for qcad. 2004-03-28 14:07:02 +02:00			`SUBDIR += qcad-partslib`
add qfsm 0.30 A graphical tool for designing finite state machines 2002-04-11 20:27:36 +02:00			`SUBDIR += qfsm`
add qmls Quine-McCluskey Logic Simplifier 2001-12-10 06:18:39 +01:00			`SUBDIR += qmls`
Graphical circuit design and simulation tool. 2005-06-11 21:53:26 +02:00			`SUBDIR += qucs`
SCEPTRE (System for Circuit Evaluation and Prediction of Transient Radiation Effects) is a general purpose circuit analysis program which provides all three major analyses, AC, DC, and transient analysis, on either linear or nonlinear networks. It employs a free-form input language and state variable methods to simulate problems of interest to electrical engineers. Requested-by: "Pedro F. Giffuni" <pfg1+@pitt.edu> 2001-02-11 07:58:11 +01:00			`SUBDIR += sceptre`
SCOTCH is a software package and libraries for graph, mesh and hypergraph partitioning, static mapping, and sparse matrix block ordering. Its purpose of Scotch is to apply graph theory, with a divide and conquer approach, to scientific computing problems such as graph and mesh partitioning, static mapping, and sparse matrix ordering, in application domains ranging from structural mechanics to operating systems or bio-chemistry. Note: there is an older tarball included in Aster's distfile, but I prefer a separate distfile from the official site. 2006-02-03 23:19:54 +01:00			`SUBDIR += scotch`
The SystemC Verification (SCV) library is an extension library to SystemC which adds advanced verification capabilities to SystemC, including constrained randomization, complex constraint solvers, data-structure creation, Transaction Level Modeling (TLM), concurrency, and dynamic resource allocation management. WWW: http://www.systemc.org/ PR: ports/106822 Submitted by: Peter Johnson 2006-12-22 10:09:38 +01:00			`SUBDIR += scv`
add slffea 1.25 San Le's Free Finite Element Analysis 2002-02-09 08:30:11 +01:00			`SUBDIR += slffea`
Sort entries. In particular, "large", "medium", "small" sort in this order, dispite their meanings. (Sometimes we're too smart for computers. :) Found by: sorting ports/INDEX by "sort -t '\|' +1 -2" (Note: the whole "x11" category appears at the end with the above sort command, but I'll leave that the way it is for now -- "ls" shows it before other x11-* entries.) 1998-12-07 03:22:12 +01:00			`SUBDIR += spice`
Add systemc 2.1.v1, a modeling platform for system-level C++ models. PR: ports/89987 Submitted by: Daniel Thiele 2005-12-18 12:23:43 +01:00			`SUBDIR += systemc`
TclSpice is an improved version of Berkeley Spice designed to be used with the Tcl/Tk scripting language. The project is open-source (BSD license) and based upon the NG-Spice source code base with many improvements Features and Improvements - Fully Tcl scriptable - installs with 'package require spice' statement - Hspice syntax (SpicePP). - GUI interfaces, various (Tk). - SpiceWish (BLT graph widget) - BLT (tcl compatible) vectors for storage, manipulation and arithmetic upon Spice waveforms. - Xspice additions (Georgia Tech). - Trigger upon waveform events. - Spice 'simulator state' save and restore for rapid 'what-if' simulations (no longer need to re-simulate from the beginning each time a device value is changed). Author: Stefan Jones <stefan.jones@multigig.com> WWW: http://tclspice.sourceforge.net/ PR: ports/99399 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru> 2006-06-26 20:34:59 +02:00			`SUBDIR += tclspice`
Activate the tkgate port. 1999-06-06 19:12:34 +02:00			`SUBDIR += tkgate`
Add new port cad/tochnog tochnog is a free finite element program with many features which is distributed under GPL. TOCHNOG accepts free format input. Boundary conditions can be imposed at geometrical entities, as well as nodes and elements. PR: 52088 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> 2003-07-13 07:29:48 +02:00			`SUBDIR += tochnog`
add transcalc 0.13 A analysis and synthesis tool for RF and microwave transmission lines 2002-09-06 11:40:18 +02:00			`SUBDIR += transcalc`
NEW port CAD/varkon A free CAD system and high level development tool for Engineering. It's a very interesting port for some branches of engineering. PR: ports/52202 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com> 2003-05-21 01:03:37 +02:00			`SUBDIR += varkon`
add vipec ViPEC is a powerful tool for the analysis of high frequency, linear electrical networks 2001-04-03 07:30:51 +02:00			`SUBDIR += vipec`
Activate xcircuit. 1998-05-18 06:21:53 +02:00			`SUBDIR += xcircuit`
Add z88 11.0, a compact Finite Element Analysis System. PR: 75698 Submitted by: Pedro F. Giffuni. 2005-01-22 17:27:18 +01:00			`SUBDIR += z88`
New cad group 1995-01-13 12:10:43 +01:00
			`.include <bsd.port.subdir.mk>`