kpriv/freebsd-ports
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
freebsd-ports/cad/Makefile

140 lines
3.2 KiB
Makefile
Raw Normal View History

Remove category pkg/COMMENT files in favour of a COMMENT variable in the category makefile. Submitted by: Matthew Seaman <m.seaman@infracaninophile.co.uk> PR: 59651
2004-04-02 09:29:48 +02:00
COMMENT = CAD tools
New port: cad/NASTRAN - NASA's classic FEA program. It's called NASTRAN-95, otherwise we cannot grab it from github "nicely". PR: 211739 Approved by: koobs
2016-08-11 18:39:29 +02:00
SUBDIR += NASTRAN-95
sort SUBDIRs.
2020-01-24 20:47:59 +01:00
SUBDIR += PrusaSlicer
New port: cad/abc: System for sequential synthesis and verification PR: 227254 Submitted by: Christian Krämer <uddka@student.kit.edu>
2018-04-24 09:53:29 +02:00
SUBDIR += abc
NEW port CAD/admesh A tool to analyze STL (stereolitholigraphy) files. PR: ports/52997 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
2003-10-10 07:16:19 +02:00
SUBDIR += admesh
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. WWW: http://mot-adms.sourceforge.net/ PR: ports/101014 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
2006-07-29 23:10:26 +02:00
SUBDIR += adms
Add cad/alliance, which is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, automatic place and route tools, and portable CMOS libraries. Approved by: linimon (mentor)
2004-05-13 20:51:03 +02:00
SUBDIR += alliance
cad/appcsxcad: New port: Minimal GUI Application using the QCSXCAD library
2021-08-19 10:45:29 +02:00
SUBDIR += appcsxcad
New port: cad/archimedes: Semiconductor device simulation software
2020-12-10 06:25:32 +01:00
SUBDIR += archimedes
Add astk-client , graphical interface for Code_Aster (client side). PR: 54765 Submitted by: thierry@pompo.net
2003-07-23 13:25:42 +02:00
SUBDIR += astk-client
Add astk-serveur 1.0.14, graphical interface for Code_Aster (server side). PR: 54764 Submitted by: thierry@pompo.net
2003-07-23 13:20:26 +02:00
SUBDIR += astk-serveur
New port atlc version 4.0.1: A tool to calculate the impedance of transmission lines Submitted by: blackend
2002-11-13 21:21:29 +01:00
SUBDIR += atlc
BasicDSP is an educational tool that makes it easy to experiment with simple Digital Signal Processing algorithms for audio signals. The input can either be taken from the sound card, or be a locally generated sine wave, white noise or impulse signal. The output is fed to the sound card, as well as to a virtual oscilloscope and spectrum analyzer.
2008-08-17 22:22:21 +02:00
SUBDIR += basicdsp
- Chase r517198 and reconnect `cad/brlcad' to the build - Remove trailing dot in two MOVED entries while I'm here
2019-11-10 10:48:36 +01:00
SUBDIR += brlcad
A Three-Dimensional Structural Finite Element Program Submitted by : Pedro F. Giffuni <giffunip@yahoo.com> Almost writeen by: maho
2003-05-05 15:06:37 +02:00
SUBDIR += calculix
cad/calculix: Split the ccx analyzer out of the main port. CalculiX has alwasy been comoposed of two independent packages: ccx and cgx. Ccx, the main tool for doing FEA, depends on fortran and currently has to be built with GCC. Cgx, on the other hand, uses OpenGL and the C++ libraries it depends on are built with our native clang so buuilding it with GCC causes C++ library conflicts. By making ccx an independent port we can better focus on the specific requirements of each tool and avoid compiler-related conflicts. This also helps the port work again with newer versions GCC. PR: 219290. 22043, 220434 Approved by: gerald
2017-08-15 02:18:22 +02:00
SUBDIR += calculix-ccx
New port: cad/caneda: EDA software suite focused on ease of use and portability
2019-11-21 08:56:02 +01:00
SUBDIR += caneda
New port cascade version 1.4: A simple tool to analyze noise and distortion of a RF system Submitted by: blackend
2002-11-13 20:12:13 +01:00
SUBDIR += cascade
New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware Research
2020-01-05 09:08:14 +01:00
SUBDIR += cascade-compiler
add chipvault 200211 A project organizer for VHDL and Verilog RTL hardware designs
2003-01-29 04:45:13 +01:00
SUBDIR += chipvault
cad/csxcad: New port: C++ library to describe geometrical objects
2021-08-19 02:27:24 +02:00
SUBDIR += csxcad
This is the new, shiny frontend for Cura. Check daid/LegacyCura for the legacy Cura that everyone knows and loves/hates. We re-worked the whole GUI code at Ultimaker, because the old code started to become unmaintainable. WWW: https://github.com/Ultimaker/Cura/wiki
2020-03-26 01:03:41 +01:00
SUBDIR += cura
cad/cura-engine: Engine of slicing solution for RepRap 3D printers The CuraEngine is a C++ console application for 3D printing GCode generation. It has been made as better and faster alternative to the old Skeinforge engine. The CuraEngine is pure C++ and uses Clipper from http://www.angusj.com/delphi/clipper.php. There are no external dependences and Clipper is included in the source code without modifications. This is just a console application for GCode generation. For a full graphical application look at https://github.com/daid/Cura with is the graphical frontend for CuraEngine. The CuraEngine can be used seperately or in other applications. Feel free to add it to your application. But to take note of the License. WWW: http://wiki.ultimaker.com/Cura PR: 192486 Submitted by: cederom tlen pl
2014-08-08 03:28:03 +02:00
SUBDIR += cura-engine
cad/cvc: New port: Circuit Validity Checker
2021-12-29 08:33:10 +01:00
SUBDIR += cvc
New port: cad/digital: Digital logic designer and circuit simulator
2019-07-22 18:31:16 +02:00
SUBDIR += digital
Add dinotrace, a mature signal waveform viewer used to debug digital design simulations. PR: ports/68688 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se>
2004-07-05 23:02:41 +02:00
SUBDIR += dinotrace
New port: cad/ecpprog: Driver for FTDI based JTAG probes, to program ECP5 FPGAs
2020-09-16 06:29:57 +02:00
SUBDIR += ecpprog
Activate Electric. PR: ports/18380 Submitted by: Mario Sergio Fujikawa Ferreira <lioux@linf.unb.br>
2000-07-30 09:14:47 +02:00
SUBDIR += electric
Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications Author: Static Free Software & Sun Microsystems, Inc. WWW: http://www.staticfreesoft.com/ PR: ports/100355 Submitted by: me (stas) Approved by: sem (mentor)
2006-09-30 11:41:07 +02:00
SUBDIR += electric-ng
cad/fasm: Make PKGBASE unique Reported by: antoine
2019-10-27 08:56:42 +01:00
SUBDIR += fasm
In preparation for Cura updates add the FDM material database
2020-03-25 19:10:50 +01:00
SUBDIR += fdm_materials
Add feappv 2.0, finite Element Analysis Program "personal version". This is a FEA program used in a classic FEM book. A complete (commercial) version is available here: <http://www.ce.berkeley.edu/~rlt/feap/> The "personal version" is very limited, but it keeps the same format as the complete (commercial) version and cad/netgen can produce files for it. PR: ports/95210 Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
2006-04-03 21:57:24 +02:00
SUBDIR += feappv
FidoCadJ is an easy to use graphical editor, with a library of electrical symbols and footprints (traditional and SMD). It aims to be an agile and effective small EDA tool for hobbyists. FidoCadJ stores its drawings in a compact text format, practical for the copy and paste in newsgroups and forums: this has determined its success on the Usenet and in numerous communities. WWW: http://davbucci.chez-alice.fr/index.php?argument=elettronica/fidocadj/fidocadj.inc
2012-05-05 18:51:14 +02:00
SUBDIR += fidocadj
(Readdition of cad/freecad which was removed on 235718) Add freecad 0.17.g20160907, general purpose 3D CAD modeller. PR: 212251 Submitted by: pfg
2016-09-08 14:17:38 +02:00
SUBDIR += freecad
The goals of the FreeHDL project are to develop a VHDL simulator that has a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage. WWW: http://www.freehdl.seul.org/ PR: ports/104634 Submitted by: lon_kamikaze at gmx.de
2006-11-05 21:51:06 +01:00
SUBDIR += freehdl
New port: cad/fritzing Fritzing is an Electronic Design Automation software with a low entry barrier, suited for the needs of designers and artists. It uses the metaphor of the breadboard, so that it is easy to transfer your hardware sketch to the software. From there it is possible to create PCB layouts for turning it into a robust PCB yourself or by help of a manufacturer. WWW: http://fritzing.org/ PR: 206697 Submitted by: lenzi.sergio@gmail.com
2016-02-01 07:23:42 +01:00
SUBDIR += fritzing
cad/gds3d: New port: Application for rendering IC (chip) layouts in 3D
2021-10-04 09:08:15 +02:00
SUBDIR += gds3d
GDSreader is a simple Calma (GDSii) parser/printer tool.
2007-04-28 18:56:55 +02:00
SUBDIR += gdsreader
GDT (graphics data text) format translator written in C/C++ that converts a binary gdsii file to a text format that is compact and easy to parse.
2007-04-29 09:20:02 +02:00
SUBDIR += gdt
Activate geda.
1998-12-06 15:13:23 +01:00
SUBDIR += geda
New/resurrected port: cad/gerbv Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are generated from PCB CAD system and sent to PCB manufacturers as basis for the manufacturing process. The standard supported by gerbv is RS-274X. The basic difference between RS-274D (the old standard) and RS-274X is basically the addition of apertures in RS-274X. It might be possible to make an RS-274X file out of an RS-274D file and an aperture list. gerbv also supports drill files. The format supported are known under names as NC-drill or Excellon. The format is a bit undefined and different EDA-vendors implement it different. But basically you need to have the tools definition in the file, then the parser is quite tolerant. The different holes are shown as dots in the (scaled) correct size. The different layers of the PCB are separated into different files. gerbv can load all files at the same time and display them "on top of each other". You can independently turn them on and off. WWW: http://gerbv.geda-project.org/ Submitted by: Ash Gokhale <ashfixit@gmail.com> Reviewed by: dmn <graahnul.grom@ya.ru>
2020-01-05 16:15:25 +01:00
SUBDIR += gerbv
Re-add cad/ghdl: GNU VHDL simulator
2019-10-23 09:13:15 +02:00
SUBDIR += ghdl
Add gmsh 1.45.1, an automatic 3D finite element mesh generator. PR: 52201 Submitted by: Pedro Giffuni <giffunip@yahoo.com>
2003-07-23 16:21:51 +02:00
SUBDIR += gmsh
add gnucap 0.30 The Gnu Circuit Analysis Package
2002-02-07 08:07:48 +01:00
SUBDIR += gnucap
[NEW PORT] cad/gplcver: A Verilog HDL simulator GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
2005-12-29 04:48:58 +01:00
SUBDIR += gplcver
New port: cad/graywolf: Fork of TimberWolf, a placement tool in VLSI design
2020-03-22 11:43:44 +01:00
SUBDIR += graywolf
This port provides a GUI for two freely available SPICE electronic circuit simulation engines: GNU-Cap and Ng-Spice. Current features: Import gschem schematic files using gentlist. Load and parse circuit description (net list) files. Provides a GUI interface for GNU-Cap OP, DC, AC and Transient analyses and generates appropriate simulator commands based on user input. Provides a GUI interface for Ng-Spice DC, AC and Transient analyses and generates appropriate simulator commands based on user input. The raw output may be viewed for any processes initiated by gspiceui. Formatting of simulator output so that it may be plotted using gwave. WWW: http://www.geda.seul.org/tools/gspiceui/index.html PR: ports/99357 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
2006-08-01 22:22:11 +02:00
SUBDIR += gspiceui
Update to latest version 3.3.39. Move to cad/gtkwave since we only have one version of this port, and the move will make maitenance easier. Approved by: kwm (mentor)
2012-09-04 10:46:18 +02:00
SUBDIR += gtkwave
New port: cad/horizon-eda: EDA package for printed circuit board design
2020-08-07 06:03:30 +02:00
SUBDIR += horizon-eda
[NEW PORT] cad/ifcopenshell: Open source IFC library and geometry engine IfcOpenShell is an open source (LGPL) software library for working with the Industry Foundation Classes (IFC) file format. Currently supported IFC releases are IFC2x3 TC1 and [IFC4 Add2 TC1]. PR: 243007 Reported by: chitty_cloud@me.com Approved by: tcberner (mentor) Differential Revision: https://reviews.freebsd.org/D24687
2020-05-23 08:57:49 +02:00
SUBDIR += ifcopenshell
add impact 0.5.3 Dynamic Finite Element Program Suite
2005-03-04 08:36:48 +01:00
SUBDIR += impact
Add chipmunk, convert to new format along the way.
1995-08-25 12:06:06 +02:00
SUBDIR += irsim
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 12:02:15 +01:00
SUBDIR += iverilog
Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability. WWW: http://www.wrcad.com/jspice3.html PR: ports/93958 Submitted by: Pedro F. Giffuni Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
2006-07-11 21:34:46 +02:00
SUBDIR += jspice3
New port: cad/k40-whisperer GUI control software for the stock K40 laser cutter controller K40 Whisperer is an alternative to the Laser Draw (LaserDRW) program that comes with some Chinese laser cutters. It reads SVG and DXF files, interprets the data and sends commands to the K40 controller to move the laser head and control the laser accordingly. K40 Whisperer does not require a USB key (dongle) to function. Features: - Reads SVG files and DXF files. - Splits input design based on color formatting (red, blue). - In SVG files blue and red paths are interpreted as vectors for vector engraving and cutting. Everything else is transferred as a raster image. - In DXF files blue paths are interpreted as vector engrave (blue). Everything else is interpreted as vector cut (red). - Performs cuts on features inside of other features before cutting the outside features. (If you cut the outside first the part might drop out of the stock material.) - Converts gray scale images to halftone images to simulating varying levels of gray (i.e. engraving pictures). The Halftone option needs to be selected under "Raster"-"Settings" to enable halftoning. WWW: http://www.scorchworks.com/K40whisperer/k40whisperer.html PR: 228466 Reviewed by: mat (mentor) Approved by: mat (mentor) Sponsored by: Warsaw Hackerspace Differential Revision: https://reviews.freebsd.org/D16339
2018-09-20 00:44:36 +02:00
SUBDIR += k40-whisperer
Add Kicad, a software for the creation of electronic schematic diagrams and printed circuit board artwork. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager.
2005-12-09 00:30:13 +01:00
SUBDIR += kicad
Add kicad-devel to the build
2009-10-27 09:26:57 +01:00
SUBDIR += kicad-devel
cad/kicad-doc: online help files and documentation for cad/kicad PR: 238678 Reported by: bob at eager dot cx
2019-06-21 15:52:01 +02:00
SUBDIR += kicad-doc
Repocopy the KiCad libraried from their -devel versions.
2018-09-24 22:50:24 +02:00
SUBDIR += kicad-library-footprints
Follow upstream and split the kicad-library-devel port into kicad-library-footprints-devel kicad-library-packages3d-devel and kicad-library-symbols-devel
2018-07-06 10:24:33 +02:00
SUBDIR += kicad-library-footprints-devel
Repocopy the KiCad libraried from their -devel versions.
2018-09-24 22:50:24 +02:00
SUBDIR += kicad-library-packages3d
Follow upstream and split the kicad-library-devel port into kicad-library-footprints-devel kicad-library-packages3d-devel and kicad-library-symbols-devel
2018-07-06 10:24:33 +02:00
SUBDIR += kicad-library-packages3d-devel
Repocopy the KiCad libraried from their -devel versions.
2018-09-24 22:50:24 +02:00
SUBDIR += kicad-library-symbols
Follow upstream and split the kicad-library-devel port into kicad-library-footprints-devel kicad-library-packages3d-devel and kicad-library-symbols-devel
2018-07-06 10:24:33 +02:00
SUBDIR += kicad-library-symbols-devel
Repocopy the KiCad libraried from their -devel versions.
2018-09-24 22:50:24 +02:00
SUBDIR += kicad-library-templates
Add a port of the KiCAD Project Templates
2018-07-28 11:49:26 +02:00
SUBDIR += kicad-library-templates-devel
Resurrect cad/klayout and update to 0.25.8.
2019-03-19 11:44:39 +01:00
SUBDIR += klayout
New port: cad/ktechlab: IDE for microcontrollers and electronics
2019-11-27 19:46:13 +01:00
SUBDIR += ktechlab
LDraw is an open standard for LEGO CAD programs that allow the user to create virtual LEGO models and scenes. You can use it to document models you have physically built, create building instructions just like LEGO, render 3D photo realistic images of your virtual models and even make animations. The possibilities are endless. Unlike real LEGO bricks where you are limited by the number of parts and colors, in LDraw nothing is impossible. WWW: http://www.ldraw.org/ PR: ports/174901 Submitted by: nemysis@gmx.ch
2013-03-13 22:39:40 +01:00
SUBDIR += ldraw
cad/ldview: New port: LDraw model viewer
2021-06-08 11:38:55 +02:00
SUBDIR += ldview
Re-add cad/leocad It was removed because of the Qt4 dependency, but the current version supports Qt5.
2019-05-18 04:51:04 +02:00
SUBDIR += leocad
New port: cad/lepton-eda The Lepton EDA suite provides schematic capture, netlisting, bill of materials generation, and many other features. It was forked from the gEDA/gaf suite in late 2016. It's in active development and well supported. WWW: https://github.com/lepton-eda/lepton-eda PR: 232076 Submitted by: dmn <graahnul.grom@gmail.com>
2019-02-23 14:49:27 +01:00
SUBDIR += lepton-eda
Libopencad is a library written in C++11, which provides a way to read/write CAD (DWG/DXF/DXFB) files. It was designed to have a uniformal API to work with any CAD files. It has a base class - CADFile. Inheriting this class it's possible to create a driver for any CAD format, all you need to do - is to overwrite interface functions like GetGeometry(index), and others. Now it has an implementation for DWG2000 (R15), but only for read. Library comes with cadinfo utility, which prints out everything library can get from file - header variables, CAD custom classes, presented layers and geometries with their attributes. WWW: https://trac.osgeo.org/gdal/wiki/DWG_driver PR: 212129 Submitted by: lbartoletti@tuxfamily.org
2016-12-26 15:29:06 +01:00
SUBDIR += libopencad
Connect librecad
2012-01-04 10:06:40 +01:00
SUBDIR += librecad
GNU LibreDWG is a C library to handle DWG files which aims to be a free replacement for the OpenDWG libraries. There are command line tools and libraries to read and write DWG files, with converters for various formats: DXF, DXFB, SVG, PS, JSON, XML, etc. WWW: https://www.gnu.org/software/libredwg/
2018-08-30 04:26:19 +02:00
SUBDIR += libredwg
New port: cad/librepcb: Schematic and PCB editing software
2019-11-23 06:11:09 +01:00
SUBDIR += librepcb
Connect cad/linux-eagle5 to the build. Forgotten by: bsam (me) Requested by: linimon
2009-11-07 10:34:31 +01:00
SUBDIR += linux-eagle5
Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits. With the capacity to build larger circuits from smaller subcircuits, and to draw bundles of wires with a single mouse drag, Logisim can be used (and is used) to design and simulate entire CPUs for educational purposes. Logisim is used by students at colleges and universities around the world in many types of classes, ranging from a brief unit on logic in general-education computer science surveys, to computer organization courses, to full-semester courses on computer architecture. WWW: http://ozark.hendrix.edu/~burch/logisim/ PR: ports/176354 Submitted by: Javad Kouhi <javad.kouhi@gmail.com>
2013-03-02 14:26:40 +01:00
SUBDIR += logisim
Add chipmunk, convert to new format along the way.
1995-08-25 12:06:06 +02:00
SUBDIR += magic
- New port: cad/meshdev MeshDev is a mesh comparison software. It accepts two meshes as input and computes the geometrical deviation between the two meshes. It return numerical values and can optionaly generate visual results (with a pseudo-colored mesh corresponding to the measured deviation) in OpenInventor format. This port features a patch (by myself) to read binary and ASCII STL files. This feature was removed in the transition from version 0.4 -> 0.5. Distfiles are unfetchable from sourceforce. For this reason, they're hosted on our infrastructure. WWW: http://meshdev.sourceforge.net/
2012-02-06 16:57:20 +01:00
SUBDIR += meshdev
cad/meshlab: Resurrect, update to 2020.05 and take maintainer'ship The project has resumed since a few months by releasing one release every month (no more beta or pre release as between 2016 and 2020). - cad/meshlab: Resurrect, update to 2020.05 and take maintainer'ship - devel/vcglib: Update to @f7871ee [1] [1] There is not new release, but Meshlab require this version PR: 217821 Reported by: pi Approved by: fernape, tcberner (mentor) Differential Revision: https://reviews.freebsd.org/D24686
2020-07-18 10:18:57 +02:00
SUBDIR += meshlab
Add netgen 4.3.1, an automatic 3D tetrahedral mesh generator.
2004-05-05 21:57:56 +02:00
SUBDIR += netgen
New port: cad/netgen-lvs: Tool for comparing netlists (a process known as LVS)
2020-03-19 04:19:57 +01:00
SUBDIR += netgen-lvs
Initial import of ngspice_rework Ngspice_rework is a circuit simulator derived from spice3f5. PR: 34589 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
2002-02-09 11:03:42 +01:00
SUBDIR += ngspice_rework
New port: cad/nvc: VHDL compiler and simulator
2019-10-23 17:08:43 +02:00
SUBDIR += nvc
Open CASCADE Technology is a software development platform freely available in open source. It includes components for 3D surface and solid modeling, visualization, data exchange and rapid application development. Open CASCADE Technology can be best applied in development of numerical simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM applications. BUGS: the module WOK does not work, but the other modules (the most interesting parts) are OK.
2007-04-01 11:04:04 +02:00
SUBDIR += opencascade
OpenCTM is a file format, a software library and a tool set for compression of 3D triangle meshes. The geometry is compressed to a fraction of comparable file formats (3DS, STL, COLLADA...), and the format is accessible through a simple, portable API WWW: https://sourceforge.net/projects/openctm/
2020-03-15 01:39:34 +01:00
SUBDIR += openctm
New port: cad/openfpgaloader: Universal utility for programming FPGA
2020-08-11 10:29:53 +02:00
SUBDIR += openfpgaloader
New port: cad/openroad: ASIC physical design tool
2020-09-14 18:15:44 +02:00
SUBDIR += openroad
Add openscad. OpenSCAD is a software for creating 3D CAD objects. Unlike most free software for creating 3D models, it does not focus on the artistic aspects of 3D modelling but instead on the CAD aspects. Thus it is more suitable for creating 3D models of machine parts but perhaps not when creating computer-animated movies. OpenSCAD is not an interactive modeller. Instead it is something like a 3D-compiler that reads in a script file that describes the object and renders the 3D model from this script file. This gives designers full control over the modelling process and enables them to easily change any step in the modelling process or make designes that are defined by configurable parameters. WWW: http://www.openscad.org/ Obtained from (slightly): OpenBSD
2011-08-19 13:02:10 +02:00
SUBDIR += openscad
Add openscad-devel to the build and register conflict.
2018-04-22 20:16:02 +02:00
SUBDIR += openscad-devel
cad/opentimer: New port: High-performance timing analysis tool for VLSI systems
2021-09-13 01:28:37 +02:00
SUBDIR += opentimer
NASA Open Source Parametric Geometry OpenVSP allows the user to create a 3D model of an aircraft defined by common engineering parameters. This model can be processed into formats suitable for engineering analysis. WWW: http://www.openvsp.org/ PR: ports/166825 Submitted by: Fernando Apesteguia <fernando.apesteguia@gmail.com>
2012-04-22 14:06:12 +02:00
SUBDIR += openvsp
Re-add cad/oregano: Schematic capture and circuit simulator
2019-11-23 19:20:17 +01:00
SUBDIR += oregano
p5-GDS2, a Perl module for quickly creating programs to read and/or write GDS2 files.
2007-04-29 09:17:29 +02:00
SUBDIR += p5-GDS2
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
SUBDIR += p5-Verilog-Perl
Add chipmunk, convert to new format along the way.
1995-08-25 12:06:06 +02:00
SUBDIR += pcb
add pdnmesh A finite element program PR: 30115 Submitted by: Sarod Yatawatta <sarod@cs.pdn.ac.lk>
2001-10-14 19:54:31 +02:00
SUBDIR += pdnmesh
Clean up some things Reported by: portscan
2020-08-18 06:11:23 +02:00
SUBDIR += py-cadquery
SUBDIR += py-cq-editor
[NEW PORT] cad/py-ezdxf: Create and modify DXF drawings A Python package to create and modify DXF drawings, independent from the DXF version. You can open/save every DXF file without losing any content (except comments), Unknown tags in the DXF file will be ignored but preserved for saving. With this behavior it is possible to open also DXF drawings that contains data from 3rd party applications. PR: 248203 Submitted by: Neal Nelson Approved by: tcberner (mentor) Differential Revision: https://reviews.freebsd.org/D25890
2020-07-30 21:43:42 +02:00
SUBDIR += py-ezdxf
Add cad/py-gdspy, Python module for creating GDSII stream files.
2016-05-16 21:48:57 +02:00
SUBDIR += py-gdspy
Add cad/py-lcapy, Symbolic MDA Analysis Package for Linear Circuits.
2016-05-16 19:34:37 +02:00
SUBDIR += py-lcapy
Clean up some things Reported by: portscan
2020-08-18 06:11:23 +02:00
SUBDIR += py-ocp
Add cad/py-phidl, a GDS-based CAD tool for photonic and superconducting circuits.
2019-03-15 14:58:32 +01:00
SUBDIR += py-phidl
New port: cad/py-pyfda: GUI tool for designing and analysing discrete time filters pyFDA allows to design digital filters for signals in digital signal processing. Screenshot: https://raw.githubusercontent.com/chipmuenk/pyFDA/master/images/pyFDA_screenshot_3.PNG The patching is mostly due to the fact that pyFDA doesn't have an installation procedure, and expects users to just run locally. PR: 222442 Submitted by: myself Approved by: adamw (mentor) Differential Revision: https://reviews.freebsd.org/D14176
2018-02-03 21:55:08 +01:00
SUBDIR += py-pyfda
cad/py-pymtl: New port: Python-based hardware generation, simulation, verification framework
2021-12-27 03:30:48 +01:00
SUBDIR += py-pymtl
Rename with python-gdsii, which is the official package name in PyPI. Suggested by: koobs
2016-11-10 20:38:43 +01:00
SUBDIR += python-gdsii
Readd qcad and upgrade to version 3.2.1 PR: ports/181199 Submitted by: Thierry Thomas (thierry@)
2013-08-21 09:52:35 +02:00
SUBDIR += qcad
cad/qcsxcad: New port: Qt-GUI for CSXCAD
2021-08-19 10:38:17 +02:00
SUBDIR += qcsxcad
QElectroTech is a Qt4 application to design electric diagrams. It uses XML files for elements and diagrams, and includes both a diagram editor and an element editor. WWW: http://qelectrotech.org/ PR: ports/146513 Submitted by: Gvozdikov Veniamin <g.veniamin at googlemail.com> Approved by: pgj (mentor)
2010-07-21 11:57:57 +02:00
SUBDIR += qelectrotech
New port: cad/qflow: End-to-end digital synthesis flow for ASIC designs
2020-03-22 11:02:44 +01:00
SUBDIR += qflow
add qmls Quine-McCluskey Logic Simplifier
2001-12-10 06:18:39 +01:00
SUBDIR += qmls
New port: cad/qrouter: Tool to generate metal layers and vias
2020-03-19 06:20:13 +01:00
SUBDIR += qrouter
RepSnapper is a host software for controlling a RepRap 3D printer. It has a 3D OpenGL interface, slices objects and calculates the extrusion toolpath. It can manipulate 3D objects and save constellations in STL and AMF format. WWW: http://reprap.org/wiki/RepSnapper_Manual:Introduction PR: ports/171796 Submitted by: Martin Dieringer <martin.dieringe@gmx.de>
2012-09-29 00:32:18 +02:00
SUBDIR += repsnapper
Add cad/rubygem-gdsii, Ruby library for GDSII reader and writer.
2016-05-16 19:37:55 +02:00
SUBDIR += rubygem-gdsii
SCOTCH is a software package and libraries for graph, mesh and hypergraph partitioning, static mapping, and sparse matrix block ordering. Its purpose of Scotch is to apply graph theory, with a divide and conquer approach, to scientific computing problems such as graph and mesh partitioning, static mapping, and sparse matrix ordering, in application domains ranging from structural mechanics to operating systems or bio-chemistry. Note: there is an older tarball included in Aster's distfile, but I prefer a separate distfile from the official site.
2006-02-03 23:19:54 +01:00
SUBDIR += scotch
cad/solvespace: create port SOLVESPACE is a parametric 3d CAD program. Applications include modeling 2d and 3d parts, 3d-printed parts, preparing CAM data, mechanism design and plane and solid geometry. WWW: http://solvespace.com/
2016-11-10 02:08:44 +01:00
SUBDIR += solvespace
Add cad/sp2sp, a command-line waveform data processor for SPICE-type simulators.
2016-11-05 19:52:36 +01:00
SUBDIR += sp2sp
Sort entries. In particular, "large", "medium", "small" sort in this order, dispite their meanings. (Sometimes we're too smart for computers. :) Found by: sorting ports/INDEX by "sort -t '|' +1 -2" (Note: the whole "x11" category appears at the end with the above sort command, but I'll leave that the way it is for now -- "ls" shows it before other x11-* entries.)
1998-12-07 03:22:12 +01:00
SUBDIR += spice
In April/May 2012, STEP Class Library was renamed to STEPcode. This was done because the old name wasn't accurate - the class libraries are only a fraction of the software. The STEP Class Library (SCL) originated at the National Institute of Standards and Technology, or NIST. NIST started working with STEP in the 80's and continued until the late 90's. Some components of SCL were originally written in Lisp and then re-written in mixed C and C++ in the early 90's. The rest of SCL was written in C++ to begin with. STEPcode (SC) includes the class libraries, some of the most widely used EXPRESS schemas, some tools to work with EXPRESS, and support libraries for those tools. Two of the tools can create schema-specific libraries that are used with the class libraries. There are also some test files and programs. WWW: https://github.com/stepcode/stepcode/wiki PR: 201046 Submitted by: fernando.apesteguia@gmail.com
2015-07-03 16:45:40 +02:00
SUBDIR += stepcode
New port: cad/stm32flash: Flash program for STM32 using the ST serial bootloader
2020-11-18 09:11:21 +01:00
SUBDIR += stm32flash
New port: cad/sumo: Traffic simulation suite for road vehicles, public transportation, etc PR: 193884 Submitted by: Enrique Fynn <me@enriquefynn.com> Approved by: tcberner (mentor) Differential Revision: https://reviews.freebsd.org/D13248
2017-12-03 20:20:35 +01:00
SUBDIR += sumo
cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
2021-12-27 18:06:26 +01:00
SUBDIR += surelog
Sweet Home 3D is a free interior design application that helps you place your furniture on a house 2D plan, with a 3D preview. WWW: http://www.sweethome3d.com PR: ports/171760 Submitted by: Matthias Petermann <matthias@petermann.it>
2013-03-21 21:16:53 +01:00
SUBDIR += sweethome3d
Restore removed cad/tkgate. - Support staging - Tested with tcl/tk 8.6 - Removed old patches - Convert to the modern port rules - Updated to version 2.0.0 (from bitbucket)
2015-06-24 16:23:14 +02:00
SUBDIR += tkgate
Add new port cad/tochnog tochnog is a free finite element program with many features which is distributed under GPL. TOCHNOG accepts free format input. Boundary conditions can be imposed at geometrical entities, as well as nodes and elements. PR: 52088 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
2003-07-13 07:29:48 +02:00
SUBDIR += tochnog
cad/uhdm: New port: Universal Hardware Data Model
2021-12-27 18:29:43 +01:00
SUBDIR += uhdm
Uranium is a Python framework for building 3D printing related applications. WWW: https://github.com/Ultimaker/uranium/wiki
2020-03-26 00:04:33 +01:00
SUBDIR += uranium
cad/verilator: create port Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng <kevinz5000@gmail.com>
2019-01-18 00:27:11 +01:00
SUBDIR += verilator
- Add port for verilog-mode.el, Emacs Verilog editing mode. WWW: http://www.veripool.org/wiki/verilog-mode
2009-01-12 10:44:37 +01:00
SUBDIR += verilog-mode.el
New port: cad/veroroute: PCB (printed circuit board) design software
2020-02-02 04:12:59 +01:00
SUBDIR += veroroute
Activate xcircuit.
1998-05-18 06:21:53 +02:00
SUBDIR += xcircuit
Move the port devel/yosys -> cad/yosys, to the proper category
2020-01-04 19:47:26 +01:00
SUBDIR += yosys
Add z88 11.0, a compact Finite Element Analysis System. PR: 75698 Submitted by: Pedro F. Giffuni.
2005-01-22 17:27:18 +01:00
SUBDIR += z88
Add a port of ZCAD, simple CAD program with AutoCAD DXF 2000 file format support. It is developed with Free Pascal and Lazarus. The project has not released any distfiles yet, so this release is based on r2259 checked out from http://svn.shamangrad.net/zcad/trunk/, cleaned up (most importantly, converted to Unix line endings), and tar+xz'ed. https://sourceforge.net/projects/zcad/
2017-05-02 20:50:35 +02:00
SUBDIR += zcad
New cad group
1995-01-13 12:10:43 +01:00
.include <bsd.port.subdir.mk>
Reference in a new issue Copy permalink